SLOS992 December   2017 TPA3156D2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Gain Setting and Master and Slave
      2. 7.3.2  Input Impedance
      3. 7.3.3  Startup and Shutdown Operation
      4. 7.3.4  PLIMIT Operation
      5. 7.3.5  GVDD Supply
      6. 7.3.6  BSPx AND BSNx Capacitors
      7. 7.3.7  Differential Inputs
      8. 7.3.8  Device Protection System
      9. 7.3.9  DC Detect Protection
      10. 7.3.10 Short-Circuit Protection and Automatic Recovery Feature
      11. 7.3.11 Thermal Protection
      12. 7.3.12 Device Modulation Scheme
        1. 7.3.12.1 BD-Modulation
      13. 7.3.13 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
      14. 7.3.14 Ferrite Bead Filter Considerations
      15. 7.3.15 When to Use an Output Filter for EMI Suppression
      16. 7.3.16 AM Avoidance EMI Reduction
    4. 7.4 Device Functional Modes
      1. 7.4.1 PBTL Mode
      2. 7.4.2 Mono Mode (Single Channel Mode)
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requriements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the PWM Frequency
        2. 8.2.2.2 Select the Amplifier Gain and Master/Slave Mode
        3. 8.2.2.3 Select Input Capacitance
        4. 8.2.2.4 Select Decoupling Capacitors
        5. 8.2.2.5 Select Bootstrap Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Mode
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Heat Sink Used on the EVM
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VCC PVCC, AVCC –0.3 30 V
Input voltage, VI INPL, INNL, INPR, INNR –0.3 6.3 V
PLIMIT, GAIN / SLV, SYNC –0.3 GVDD+0.3 V
AM0, AM1, AM2, MUTE, SDZ, MODSEL –0.3 PVCC+0.3 V
Slew rate, maximum(2) AM0, AM1, AM2, MUTE, SDZ, MODSEL 10 V/ms
Operating free-air temperature, TA –40 85 °C
Operating junction temperature , TJ –40 150 °C
Storage temperature, Tstg –40 125 °C
(1) Stresses beyond those listed under absolute maximum ratings can cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.
(2) 100-kΩ series resistor is required if maximum slew rate is exceeded.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. .

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage PVCC, AVCC 4.5 26 V
VIH High-level input voltage AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL 2 V
VIL Low-level input voltage AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL 0.8 V
VOL Low-level output voltage FAULTZ, RPULL-UP = 100 kΩ, PVCC = 26 V 0.8 V
IIH High-level input current AM0, AM1, AM2, MUTE, SDZ, MODSEL
(VI = 2 V, VCC = 18 V)		 50 µA
RL(BTL) Minimum load Impedance Output filter: L = 10 µH, C = 680 nF 3.2 4 Ω
RL(PBTL) Output filter: L = 10 µH, C = 1 µF 1.6 2
Lo Output-filter Inductance Minimum output filter inductance under short-circuit condition 1 µH

6.4 Thermal Information

THERMAL METRIC(1) TPA3156D2 UNIT
DAD(2)
32 PINS
RθJA Junction-to-ambient thermal resistance N/A °C/W
RθJC(top) Junction-to-case (top) thermal resistance 1.2 °C/W
ψJT Junction-to-top characterization parameter 1.2 °C/W
ψJB Junction-to-board characterization parameter 21 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For the PCB layout please see the TPA3156D2EVM user guide.

6.5 DC Electrical Characteristics

TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω, fs = 400 kHz, low idle-loss mode(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
| VOS | Class-D output offset voltage (measured differentially) VI = 0 V 1.5 5 mV
ICC Quiescent supply current SDZ = 2 V, With load and filter, PVCC = 12 V 15 mA
SDZ = 2 V, With load and filter, PVCC = 24 V 23
ICC(SD) Quiescent supply current in shutdown mode SDZ = 0.8 V, With load and filter, PVCC = 12 V 20 µA
SDZ = 0.8 V, With load and filter, PVCC = 24 V 30
rDS(on) Drain-source on-state resistance, measured pin to pin PVCC = 21 V, Iout = 500 mA, TJ = 25°C 90 mΩ
G Gain (BTL) R1 = 5.6 kΩ, R2 = Open 19 20 21 dB
R1 = 20 kΩ, R2 = 100 kΩ 25 26 27
R1 = 39 kΩ, R2 = 100 kΩ 31 32 33 dB
R1 = 47 kΩ, R2 = 75 kΩ 35 36 37
G Gain (SLV) R1 = 51 kΩ, R2 = 51 kΩ 19 20 21 dB
R1 = 75 kΩ, R2 = 47 kΩ 25 26 27
R1 = 100 kΩ, R2 = 39 kΩ 31 32 33 dB
R1 = 100 kΩ, R2 = 16 kΩ 35 36 37
ton Turn-on time SDZ = 2 V 40 ms
tOFF Turn-off time SDZ = 0.8 V 2 µs
GVDD Gate drive supply IGVDD < 200 µA 5.1 5.6 6.3 V
VO Output voltage maximum under PLIMIT control V(PLIMIT) = 2 V; VI = 1 Vrms 6.75 8.2 8.75 V

6.6 AC Electrical Characteristics

TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
KSVR Power supply ripple rejection 200 mVPP ripple at 1 kHz, Gain = 26 dB, Inputs
AC-coupled to GND		 –70 dB
PO Continuous output power THD+N = 10%, f = 1 kHz, PVCC = 14.4 V, Load = 4Ω 25 W
THD+N = 10%, f = 1 kHz, PVCC = 21 V, Load = 8 Ω 50
THD+N = 10%, f = 1 kHz, PVCC = 24 V, Load = 4 Ω 70
THD+N Total harmonic distortion + noise VCC = 21 V, f = 1 kHz, PO = 15 W (half-power) 0.1%
Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB 65 µV
–80 dBV
Crosstalk VO = 1 Vrms, Gain = 20 dB, f = 1 kHz –100 dB
SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted 102 dB
fOSC Oscillator frequency AM2=0, AM1=0, AM0=0 376 400 424 kHz
AM2=0, AM1=0, AM0=1 470 500 530
AM2=0, AM1=1, AM0=0 564 600 636
AM2=0, AM1=1, AM0=1 940 1000 1060
AM2=1, AM1=0, AM0=0 1128 1200 1278
AM2=1, AM1=0, AM0=1 282 300 318
AM2=1, AM1=1, AM0=0 282 300 318
Modulation scheme Fixed in 1SPW Mode
AM2=1, AM1=1, AM0=1 Reserved
Thermal trip point ≥150 °C
Thermal hysteresis 15 °C
Over current trip point 10 A

6.7 Typical Characteristics

fs = 400 kHz, Ultra Low Idle Loss Mode, TPA3156D2EVM Tested With AP2722. (unless otherwise noted)
TPA3156D2 D002-SLOS992.gif Figure 1. Idle Current vs PVCC
TPA3156D2 D006_SLOS941.gif Figure 3. Total Harmonic Distortion + Noise (BTL) vs Frequency
TPA3156D2 D008_SLOS941.gif Figure 5. Total Harmonic Distortion + Noise (BTL) vs Output Power
TPA3156D2 D010_SLOS941.gif Figure 7. Total Harmonic Distortion + Noise (BTL) vs Output Power
TPA3156D2 D012_SLOS941.gif Figure 9. Output Power (BTL) vs Plimit Voltage
TPA3156D2 D014_SLOS941.gif Figure 11. Maximum Output Power (BTL) vs Supply Voltage
TPA3156D2 D016_SLOS941.gif Figure 13. Power Efficiency (BTL) vs Output Power
TPA3156D2 D001-SLOS992.gif Figure 15. Crosstalk vs Frequency
TPA3156D2 D020_SLOS941.gif Figure 17. Supply Ripple Rejection Ratio (BTL) vs Frequency
TPA3156D2 D022_SLOS941.gif Figure 19. Total Harmonic Distortion + Noise (PBTL) vs Output Power
TPA3156D2 D024_updated_SLOS941.gif Figure 21. Power Efficiency (PBTL) vs Output Power
TPA3156D2 D003-SLOS992.gif Figure 23. Total Harmonic Distortion + Noise (PBTL) vs Output Power
TPA3156D2 D005_SLOS941.gif Figure 2. Total Harmonic Distortion + Noise (BTL) vs Frequency
TPA3156D2 D007_SLOS941.gif Figure 4. Total Harmonic Distortion + Noise (BTL) vs Output Power
TPA3156D2 D009_SLOS941.gif Figure 6. Total Harmonic Distortion + Noise (BTL) vs Output Power
TPA3156D2 D011_SLOS941.gif Figure 8. Total Harmonic Distortion + Noise (BTL) vs Output Power
TPA3156D2 D013_SLOS941.gif Figure 10. Gain/Phase (BTL) vs Frequency
TPA3156D2 D015_SLOS941.gif Figure 12. Maximum Output Power (BTL) vs Supply Voltage
TPA3156D2 D017_SLOS941.gif Figure 14. Power Efficiency (BTL) vs Output Power
TPA3156D2 D019_SLOS941.gif Figure 16. Crosstalk vs Frequency
TPA3156D2 D021_SLOS941.gif Figure 18. Total Harmonic Distortion + Noise (PBTL) vs Frequency
TPA3156D2 D023_updated_SLOS941.gif Figure 20. Maximum Output Power (PBTL) vs Supply Voltage
TPA3156D2 D025_SLOS941.gif Figure 22. Supply Ripple Rejection Ratio (PBTL) vs Frequency
TPA3156D2 D004-SLOS992.gif Figure 24. Maximum Output Power (PBTL) vs Supply Voltage