SLIS170 December   2015 TPIC2010

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - Serial Port Voltage Levels
    6. 7.6  Electrical Characteristics - Common Part
    7. 7.7  Electrical Characteristics - Charge Pump
    8. 7.8  Electrical Characteristics - V1pXV DC-DC Converter
    9. 7.9  Electrical Characteristics - 3.3-V DC-DC Converter
    10. 7.10 Electrical Characteristics - Spindle Motor Driver Part
    11. 7.11 Electrical Characteristics - Sled Motor Driver Part
    12. 7.12 Electrical Characteristics - Focus/Tilt/Tracking/Driver Part
    13. 7.13 Electrical Characteristics - Load Driver Part
    14. 7.14 Electrical Characteristics - Stepping Motor Driver Part
    15. 7.15 Electrical Characteristics - Current Switch Part
    16. 7.16 Electrical Characteristics - LED Switch Part
    17. 7.17 Electrical Characteristics - Thermometer Part
    18. 7.18 Electrical Characteristics - Actuator Protection
    19. 7.19 Serial Port I/F Write Timing Requirements
    20. 7.20 Serial Port I/F Read Timing Requirements
    21. 7.21 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection Functions
        1. 8.3.1.1 Undervoltage Lockout (UVLO)
        2. 8.3.1.2 Overvoltage Protection (OVP)
        3. 8.3.1.3 Overcurrent Protection (OCP)
        4. 8.3.1.4 Thermal Protection (TSD)
        5. 8.3.1.5 Actuator Temperature Protection (ACTTIMER)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset (POR)
        1. 8.4.1.1 Power-Up Sequences
        2. 8.4.1.2 XRESET
    5. 8.5 Programming
      1. 8.5.1 Function and Operation
        1. 8.5.1.1 Serial Port Functional Description
        2. 8.5.1.2 Write Operation
        3. 8.5.1.3 Read Operation
        4. 8.5.1.4 Write and Read Operation
    6. 8.6 Register Maps
      1. 8.6.1 Register State Transition
      2. 8.6.2 DAC Register (12-Bit Write Only)
      3. 8.6.3 Control Register (8-Bit Read/Write)
      4. 8.6.4 Detailed Description of Register
        1. 8.6.4.1  REG01 12-Bit DAC for Tilt
        2. 8.6.4.2  REG02 12-Bit DAC for Focus
        3. 8.6.4.3  REG03 12-Bit DAC for Tracking
        4. 8.6.4.4  REG04 12-Bit DAC for Sled1
        5. 8.6.4.5  REG05 12-Bit DAC for Sled2
        6. 8.6.4.6  REG06 12-Bit DAC for Stepping1
        7. 8.6.4.7  REG07 12-Bit DAC for Stepping2
        8. 8.6.4.8  REG08 12-Bit DAC for Spindle
        9. 8.6.4.9  REG09 12-Bit DAC for Load
        10. 8.6.4.10 REG63 8-Bit Control Register for SpinAdj
        11. 8.6.4.11 REG6C 8-Bit Control Register for EDetCfg
        12. 8.6.4.12 REG6D 8-Bit Control Register for DCCfg
        13. 8.6.4.13 REG6E 8-Bit Control Register for UtilCfg
        14. 8.6.4.14 REG6F 8-Bit Control Register for MonitorSet
        15. 8.6.4.15 REG70 8bit Control Register for DriverEna
        16. 8.6.4.16 REG71 8-Bit Control Register for FuncEna
        17. 8.6.4.17 REG72 8-Bit Control Register for ACTCfg
        18. 8.6.4.18 REG73 8-Bit Control Register for Parm0
        19. 8.6.4.19 REG74 8-Bit Control Register for SIFCfg
        20. 8.6.4.20 REG76 8-Bit Control Register for WriteEna
        21. 8.6.4.21 REG77 8-Bit Control Register for ClrReg
        22. 8.6.4.22 REG78 8-Bit Control Register for ActTemp
        23. 8.6.4.23 REG79 8-Bit Control Register for UVLOMon
        24. 8.6.4.24 REG7A 8-Bit Control Register for ThPMon
        25. 8.6.4.25 REG7B 8-Bit Control Register for OCPMon
        26. 8.6.4.26 REG7C 8-Bit Control Register for TempMon
        27. 8.6.4.27 REG7E 8-Bit Control Register for Version (REG7E)
        28. 8.6.4.28 REG7F 8-Bit Control Register for Status (REG7F)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  DAC Type
      2. 9.1.2  Example Sampling Rate of 12-Bit DAC for FCS/TRK/TLT
      3. 9.1.3  Digital Input Coding
      4. 9.1.4  Example Timing of Target Control System
      5. 9.1.5  Spindle Motor Driver Part
        1. 9.1.5.1 Spindle PWM Control
        2. 9.1.5.2 Auto Short Brake Function
        3. 9.1.5.3 Spindle Low Speed Mode
        4. 9.1.5.4 Spindle Driver Current Limiting Circuit
      6. 9.1.6  Sled Driver Part
        1. 9.1.6.1 End Detect Function
      7. 9.1.7  Load Driver Part
      8. 9.1.8  Focus/Track/Tilt Driver Part
        1. 9.1.8.1 Input vs Output Duty
        2. 9.1.8.2 Differential Tilt Mode
      9. 9.1.9  2-Channel Synchronous DC-DC Converter
        1. 9.1.9.1 V1Px DC-DC Converter
        2. 9.1.9.2 V3P3 DC-DC Converter
        3. 9.1.9.3 Setup When Not Using DC-DC Converter
        4. 9.1.9.4 Discontinuous Regulation Mode
      10. 9.1.10 Monitor Signal on GPOUT
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

TPIC2010 is low noise type motor driver IC suitable for 5V optical disk drives. The 9-channel driver IC controlled by SPI is optimum for driving a spindle motor, a sled motor (stepping motor applicable), a load motor, and Focus / Tracking / Tilt actuators and stepping motor for collimator lens. This IC requires an external current sense resistance to measure SPM current. The spindle motor driver part uses integrated sensorless logic to attain low-noise operation during startup and runtime. By using BEMF feedback, external sensors, such as a Hall device, are not needed to carry out self-starting by the starting circuit or perform position detection. By using the efficient PWM drivers, low-power operation can be achieved by controlling the PWM outputs. Dead zone less control is possible for a Focus / Tracking / Tilt actuator driver. In addition, the spindle part output current limiting circuit, the thermal shut down circuit, the sled end detection circuit, collimator lens end detection circuits offer protection for all actuators and motors.

8.2 Functional Block Diagram

TPIC2010 fbd_slis170.gif

8.3 Feature Description

8.3.1 Protection Functions

TPIC2010 has five protection features: undervoltage lockout, overvoltage protection (OVP), over currentprotection (OCP), thermal protection (TSD), and actuator temperature protection (ACTTIMER) in order to protect target equipment. A protect behavior differ by generated events.

8.3.1.1 Undervoltage Lockout (UVLO)

Power Faults are reported in the UVLOMon register. Each UVLOMon bit will be initialized to zero upon a cold power up. After a fault is detected the appropriate fault bit will be latched high. Writing to the RST_ERRFLG (REG77) will clear all UVLOMon bits. The power device faults and actions are summarized in Table 1.

Table 1. Power Fault Monitor

FAULT TYPE LATCHED REGISTER XRESET CRITERIA SPM ACTUATOR DC-DC
A5V under voltage UVLO_A5V Yes <3.7 V Hi-Z Hi-Z Hi-Z
Feedback pin to GND
internal 3.3V under voltage UVLO_INT3P3 Yes <2.7 V Hi-Z Hi-Z Hi-Z
3.3V DC-DC output under voltage UVLO_SWR3P3 Yes <80% Hi-Z Hi-Z
1.xV DC-DC output under-voltage UVLO_SWR1PX Yes <80% Hi-Z Hi-Z
P5V over-voltage OVP_P5V >6.2 V Brake
>6.5 V Hi-Z Hi-Z Hi-Z

8.3.1.2 Overvoltage Protection (OVP)

Over voltage protect function is aimed to protect the unit from the supplying hi-voltage.

When the supply voltage exceeds 6.5 V, all driver and DC-DC converter output goes Hi-Z. When the supply voltage falls below typical 6.2 V, (6.0 V for SPM) all output start to operate again. The OVP and POR (XRESET) function is not interlocking. However, DC-DC converter output falls by Hi-Z operations, output voltage falls to 80% then XRESET signal goes low.

Moreover, when power supply exceeds 6.2 V, especially SPM enter short brake mode. This operation is offered supposing a voltage rising by motor BEMF of the high velocity revolution.

This function is for insurance, so it can not assure that the device is safety in the condition. Because the absolute maximum ratings range of the supply voltage is 6 V. When this function works, the feed back terminals are not shorted to GND.

Figure 6 shows the behavior of OVP.

TPIC2010 OVP_lis170.gif Figure 6. Overvoltage Protection

8.3.1.3 Overcurrent Protection (OCP)

The OCP function serve to protect the device from break down by large current. The OCP is provided for five circuit blocks, and each threshold are in Table 2.

Table 2. OCP Threshold

BLOCK DETECTION CURRENT MONITOR TIME HI-Z HOLD TIME
DC-DC conv V1PX
V3P3
1850 mA 1 ms POR
1150 mA 1 ms POR
LOAD driver 1 ch
0.5 ch
100% 800 ms Forever
260 mA 800 ms Forever
STEP driver 850 mA 1 µs 25 ms
LED driver 100 mA 20 µs 0.4 ms
CSW driver 1000 mA 20 µs 1.6 ms

When the large current is detected on each block, device put the output FET to Hi-Z.

The amounts of currents and time have specified the detection threshold for every circuit block.

When OCP occurs, it returns automatically after expiring set Hi-Z period. However, it restricts, the POR is performed at OCP for DC-DC converter. It keeps XRESET=L and does not return forever. It’s necessary power ON/OFF actuation in order to make it release.

OCPERR (REG7F) and OCP flag (REG7B) are set at OCP detection.

TPIC2010 ocp_prot_DCDC_lis170.gif Figure 7. OCP DC-DC Converter
TPIC2010 ocp_load_1_lis170.gif Figure 8. OCP Load 1-Channel
TPIC2010 ocp_load_0p5_lis170.gif Figure 9. OCP Load 0.5-Channel
TPIC2010 ocp_step_lis170.gif
STP1 and STP2 channel has current trip function. The output of STEP channel will be changed Hi-Z if current exceed current limit threshold (850-mA typ). When the trip period 25ms is expired, trip state is automatically released.
Figure 10. OCP Step
TPIC2010 ocp_LED_lis170.gif Figure 11. OCP LED Driver
TPIC2010 ocp_curr_sw_lis170.gif Figure 12. OCP Current Switch

8.3.1.4 Thermal Protection (TSD)

The thermal protection (TSD) is a protect function which intercepts an output and suspends an operation when the IC temperature exceed a maximum permissible on a safety. TSD makes an output Hi-Z when the temperature rises up and a threshold value is exceeded. There’re two levels for threshold “Alert” and “Trip”. Alarm is given by status register “TSD_FAULT_” on “Alert” level with 135°C. It continues rising up temperature, the register “TSD_” is set at 150°C and the driver output changes HI-Z. If temperature falls and is reached 135°C, it will output again. TPIC2010 has total 12 temperature sensors in each circuit block. Particular sensor is assigned to appropriate status flag in List 10 OCP threshold.

Table 3. Thermal Sensor Assignment

CIRCUIT ALERT (°C) TRIP (°C) RELEASE (°C) ALERT FLAG TRIP FLAG
U 130 145 130 TSD_FAULT_SPM TSD_SPM
V 130 145 130 TSD_FAULT_SPM TSD_SPM
W 130 145 130 TSD_FAULT_SPM TSD_SPM
TLT 130 145 130 TSD_FAULT_ACT TSD_ACT
FCS 130 145 130 TSD_FAULT_ACT TSD_ACT
TRC 130 145 130 TSD_FAULT_ACT TSD_ACT
SLED1 130 145 130 TSD_FAULT_ACT TSD_ACT
SLED2 130 145 130 TSD_FAULT_ACT TSD_ACT
STP 130 145 130 TSD_FAULT_ACT TSD_ACT
LOAD 130 145 130 TSD_FAULT_ACT TSD_ACT
LED/CSW 130 145 130 TSD_FAULT_LEDCSW TSD_ LEDCSW
2ch DCDC 130 145 130 TSD_FAULT_SWR TSD_SWR

8.3.1.5 Actuator Temperature Protection (ACTTIMER)

TPIC2010 has Actuator protect function named ACTTIMER. This function enables to avoid from being broken by setting actuator channel output to HIZ when actuator coil current exceeds the specific value. Up to now, be used a simple actuator protect function such like exceeding max current with continuous time. However these types were not accurate. This new protection enables to calculate heat accumulation and judge correctly. When this function operates, load channel output will be Hi-Z, too. And spindle channel will be forced “Auto short brake” and disc motor will stop.

It’s able to know the protection has occurred by checking Fault register ACTTIMER_FAULT (REG7F) and ACT_TIMER_PROT (REG78). ACTTIMER_FAULT has a character of advance notice, is set before detecting ACT_TIMER_PROT. Once an ACT_TIMER_PROT is set, even if temperature falls, it will not release protection automatically. It’s necessary to clear the flag by setting RST_ERR_FLAG (REG77) or setting 0 to ACTTEMPTH (REG72). ACTTIMER function is able to disable by setting H to ACTPROT_OFF (REG72) or setting 0 to ACTTEMPTH (REG72).

In order to acquire the optimal value for ACTTEMPTH, you should set device into the condition of the detection level, and reading the value of ACTTEMP. Because of the present value can be read from ACTTEMP (REG78). (1)

(1)The ACTTEMP data is updated on Register in ACTPROT_OFF = 0 and ACTTEMPTH > 0.
TPIC2010 actuator_temp_prt_lis170.gif Figure 13. Actuator Temperature Protections

8.4 Device Functional Modes

8.4.1 Power-On Reset (POR)

8.4.1.1 Power-Up Sequences

The power up sequence is described in Table 4.

In TPIC2010, the normal sequence is to wait for 5-V supply to come up to 3.9 V. After 5 V establish, the internal 3.3 V will stabilize. Now the voltage monitors start to work and begin to look for the DC-DC V1Px and V3P3. Start up sequence for internal DC-DC converter is selected by external pin, SWR_SEQ1 and SWR_SEQ2. All DC-DC converters stabilize the power up sequence finishes and the part starts to function. Once the part finishes all of its power up tasks, it takes XRESET high to indicate that the part is no longer in reset and ready to communicate to the outside world. All the DC-DC converter have soft-start features to avoid rush current and voltage over shoot. Each soft-start sequence takes about 0.8 ms.

Table 4. DC-DC Start-Up Sequence and Output

V1PXSEL SWR_SEQ2 SWR_SEQ1 REG1PX(V) REG3P3(V) SEQUENCE
REG1PX REG3P3
0 0 0 1.2 3.3 Same
0 0 1 1.2 3.3 2nd 1st
0 1 0 1.2 3.3 1st 2nd
0 1 1 1.0 3.3 Same
1 0 0 1.5 3.3 Same
1 0 1 1.5 3.3 2nd 1st
1 1 0 1.5 3.3 1st 2nd
1 1 1 Disable(1)
(1) This setting is able to use REG1PX, REG3P3 pin as GPOUT pin.
TPIC2010 simul_start_lis170.gif Figure 14. Simultaneously Start Up (SWR_SEQ[1:0] = 00)
TPIC2010 tim_V1Px_lis170.gif Figure 15. V1Px Start First (SWR_SEQ[1:0] = 10)
TPIC2010 tim_V3P3_start_lis170.gif Figure 16. V3P3 Start First (SWR_SEQ[1:0] = 01)

8.4.1.2 XRESET

TPIC2010 is preparing XRESET pin in order to notify an own status to DSP. TPIC2010 set XRESET to L when the event which has a serious effect on DSP occurs such like the power failure, the over temperature and the drop of DC-DC converter output. If all the exception is removed, it will tell that XRESET pin would be set to H and it would be in the ready state. The POR (power on reset) condition is shown in Figure 17. All the behavior of XRESET is shown in Figure 21.

TPIC2010 fbd_POR_lis170.gif Figure 17. POR Block Diagram
TPIC2010 5_supply_V_lis170.gif Figure 18. 5-V Supply Voltage Drop
TPIC2010 3p3_out_V_drop_lis170.gif Figure 19. 3.3-V Output Voltage Drops (SWR_SEQ = 00, 11)
TPIC2010 1px_out_V_drop_lis170.gif Figure 20. 1.x V Output Voltage Drops (SWR_SEQ = 00, 11)
TPIC2010 XRESET_behavior_lis170.gif
1. The period of XMUTE = L cannot be communicated with device.
2. DC-DC converter disable is V1PXSEL = H, SWR_SEQ1 = H, SWR_SEQ2 = H
3. When exceed 6.5 V, DC-DC converter output changed Hi-Z and output falling < 80%. Consequently force RESET event. (Released > 90%)
Figure 21. XRESET Behavior

8.5 Programming

8.5.1 Function and Operation

8.5.1.1 Serial Port Functional Description

The serial communication of TPIC2010 is based on a SPI communications protocol. TPIC2010 is put on the slave side. All 16-bit transmission data is effective in SSZ = L period.

The bit stream sent through SIMO from a master (DSP) is latched to an internal shift register by the rising edge of SCLK. All the data is transmitted in a total of 16-bit format of a command and data. A format has two types of data, 8 bits and 12 bits length. In order to access specific registers, an address and R/W flag are specified as a command part. In addition, 12 bit data do not have R/W flag in the packet because DAC register (= 12-bit data form) are Write only. A transfer packet, command and data, is transmitted sequentially from MSB to LSB. A packet is distinguished in MSB 2 bits of command. In the case of 11, it handles a packet for control register access, and the other processed as a packet for a DAC data setting.

There are the following four kinds of serial-data communication packets.

  1. Write 12 bits DAC data (MSB two bit ≠ 11)
  2. Write 8 bits control register (MSB two bit = 11)
  3. Read 8 bits control register (MSB two bit = 11)
  4. Write 12 bits Focus DAC data+Read 8 bits status register at the same time (MSB two bit ≠ 11)

8.5.1.2 Write Operation

For write operation, DSP transmits 16 bit (command + address + data) data a bit every in an order from MSB. Only the 16-bit data which means 16 SCLK sent from the master during SSZ = L becomes effective. If more than 17 or less than 15 SCLK pulses are received during the time that SSZ is low, the whole packet will be ignored. For all valid write operations, the data of the shift register is latched into its designated internal register at rising edge of 16th SCLK. All internal register bits, except indicated otherwise, are reset to their default states upon power-on-reset.

TPIC2010 tim_write_12b_lis170.gif Figure 22. Write 12 Bits DAC Data
TPIC2010 tim_write_8b_lis170.gif Figure 23. Write 8 Bits Control Register

8.5.1.3 Read Operation

DSP sends 8-bit header through SIMO, in order to perform Read operation. TPIC2010 will start to drive the SOMI line upon the eighth falling edge of SCLK and shift out eight data bits. The master DSP inputs 8bits data from SOMI after the ninth rising edge of SCLK.   There’s optional read mode that SOMI data is advanced a half clock cycle of SCLK. This mode becomes effective by setting “ADVANCE_RD” (REG74) = H.

TPIC2010 tim_read_8b_lis170.gif Figure 24. Read 8 Bits Control Register

8.5.1.4 Write and Read Operation

Optionally, the master DSP can read Status register during writing 12 bits DAC (Focus DAC) packet. It’s enabled by setting bit “RDSTAT_ON_VFCS” (REG74) = H.

TPIC2010 tim_write_12b_Focus_lis170.gif Figure 25. Write 12 Bits Focus DAC Data + Read 8 Bits Status Data

8.6 Register Maps

All registers are in WRITE-protect mode after XRESET release. “WRITE_ENA” bit (REG76) = H is required before writing data in register.

8.6.1 Register State Transition

TPIC2010 reg_state_trans_lis170.gif
1. When exceed 6.5 V, DC-DC converter output changed Hi-Z and output falling <80%.
2. All register except CSW, LED, and XSLEEP is initialized.
Figure 26. Register State Transition Chart

8.6.2 DAC Register (12-Bit Write Only)

Two difference forms are prepared in 12-bit DAC register, and the forms can be selected by setting VDAC_MAPSW (REG74h).

Table 5. DAC Register (VDAC_MAPSW = 0)

REG NAME F 11 10 9 8 7 6 5 4 3 2 1 0
00h N/A W N/A N/A N/A
01h VTLT W VTLT[11] VTLT[10] VTLT[9] VTLT[8] VTLT[7] VTLT[6] VTLT[5] VTLT[4] VTLT[3] VTLT[2] VTLT[1] VTLT[0]
02h VFCS W VFCS[11] VFCS[10] VFCS[9] VFCS[8] VFCS[7] VFCS[6] VFCS[5] VFCS[4] VFCS[3] VFCS[2] VFCS[1] VFCS[0]
03h VTRK W VTRK[11] VTRK[10] VTRK[9] VTRK[8] VTRK[7] VTRK[6] VTRK[5] VTRK[4] VTRK[3] VTRK[2] VTRK[1] VTRK[0]
04h VSLD1 W VSLD1[11] VSLD1[10] VSLD1[9] VSLD1[8] VSLD1[7] VSLD1[6] VSLD1[5] VSLD1[4] VSLD1[3] VSLD1[2] VSLD1[1](1) VSLD1[0](1)
05h VSLD2 W VSLD2[11] VSLD2[10] VSLD2[9] VSLD2[8] VSLD2[7] VSLD2[6] VSLD2[5] VSLD2[4] VSLD2[3] VSLD2[2] VSLD2[1](1) VSLD2[0](1)
06h VSTP1 W VSTP1[11] VSTP1[10] VSTP1[9] VSTP1[8] VSTP1[7] VSTP1[6] VSTP1[5] VSTP1[4] VSTP1[3](1) VSTP1[2](1) VSTP1[1](1) VSTP1[0](1)
07h VSTP2 W VSTP2[11] VSTP2[10] VSTP2[9] VSTP2[8] VSTP2[7] VSTP2[6] VSTP2[5] VSTP2[4] VSTP2[3](1) VSTP2[2](1) VSTP2[1](1) VSTP2[0](1)
08h VSPM W VSPM[11] VSPM[10] VSPM[9] VSPM[8] VSPM[7] VSPM[6] VSPM[5] VSPM[4] VSPM[3] VSPM[2] VSPM[1] VSPM[0]
09h VLOAD W VLOAD[11] VLOAD[10] VLOAD[9] VLOAD[8] VLOAD[7] VLOAD[6] VLOAD[5] VLOAD[4] VLOAD[3] VLOAD[2] VLOAD[1] VLOAD[0]
0Ah N/A W N/A N/A N/A
0Bh N/A W N/A N/A N/A
(1) TPIC2010 process as 0 even if set as 1.

Table 6. DAC Register (VDAC_MAPSW = 1)

REG NAME F 11 10 9 8 7 6 5 4 3 2 1 0
00h N/A W N/A N/A N/A
01h VTLT W VTRK[11] VTRK[10] VTRK[9] VTRK[8] VTRK[7] VTRK[6] VTRK[5] VTRK[4] VTRK[3] VTRK[2] VTRK[1] VTRK[0]
02h VFCS W VFCS[11] VFCS[10] VFCS[9] VFCS[8] VFCS[7] VFCS[6] VFCS[5] VFCS[4] VFCS[3] VFCS[2] VFCS[1] VFCS[0]
03h VTRK W VTLT[11] VTLT[10] VTLT[9] VTLT[8] VTLT[7] VTLT[6] VTLT[5] VTLT[4] VTLT[3] VTLT[2] VTLT[1] VTLT[0]
04h VSLD1 W VSLD1[11] VSLD1[10] VSLD1[9] VSLD1[8] VSLD1[7] VSLD1[6] VSLD1[5] VSLD1[4] VSLD1[3] VSLD1[2] VSLD1[1](1) VSLD1[0](1)
05h VSLD2 W VSLD2[11] VSLD2[10] VSLD2[9] VSLD2[8] VSLD2[7] VSLD2[6] VSLD2[5] VSLD2[4] VSLD2[3] VSLD2[2] VSLD2[1](1) VSLD2[0](1)
06h VSTP1 W VSPM[11] VSPM[10] VSPM[9] VSPM[8] VSPM[7] VSPM[6] VSPM[5] VSPM[4] VSPM[3] VSPM[2] VSPM[1] VSPM[0]
07h VSTP2 W N/A N/A N/A
08h VSPM W N/A N/A N/A
09h VLOAD W N/A VLOAD[11] VLOAD[10] VLOAD[9] VLOAD[8] VLOAD[7] VLOAD[6] VLOAD[5] VLOAD[4]
0Ah N/A W N/A VSTP1[11] VSTP1[10] VSTP1[9] VSTP1[8] VSTP1[7] VSTP1[6] VSTP1[5] VSTP1[4]
0Bh N/A W N/A VSTP2[11] VSTP2[10] VSTP2[9] VSTP2[8] VSTP2[7] VSTP2[6] VSTP2[5] VSTP2[4]
(1) TPIC2010 process as 0 even if set 1.

8.6.3 Control Register (8-Bit Read/Write)

Table 7. Control Register(1)

REG NAME F 7 6 5 4 3 2 1 0
70h DriverEna R/W TLT_ENA FCS_ENA TRK_ENA SPM_ENA SLD_ENA STP_ENA LOAD_ENA XSLEEP
71h FuncEna R/W SPM_LSMODE ENDDET_ENA ENDDET_SLCT LED_ON CSW_ON TEMPMON_ENA TI reserved
72h ACTCfg R/W LOAD_O5CH_HIGH LOADPROT_OFF ACTPROT_OFF ACTTEMPTH
73h Parm0 R/W SIF_TIMEOUT_TH SLDEND_HZTIME SLDENDTH STPEND_HZTIME STPENDTH
74h SIFCfg R/W DIFF_TLT LOAD05_CH RDSTAT_ON_VFCS VSLD2_POL VSTP2_POL ADVANCE_RD SOMI_HIZ VDAC_MAPSW
75h Protect R/W TI reserved
76h WriteEna R/W WRITE_ENABLE TI reserved REG6X_WR
77h ClrReg W RST_INDAC RST_REGS RST_ERR_FLAG RST_REGS_WO3 TI reserved
78h ActTemp R TI reserved ACT_TIMER_PROT ACTTEMP
79h UVLOMon R TI reserved UVLO_A5V UVLO_INT3P3 UVLO_SWR3P3 UVLO_SWR1PX OVP_P5V
7Ah ThPMon R TSD_FAULT_SWR TSD_FAULT_SPM TSD_FAULT_ACT TSD_FAULT_LEDCSW TSD_SWR TSD_SPM TSD_ACT TSD_ LEDCSW
7Bh OCPMon R TI reserved OCP_SWR OCP_STP OCP_LOAD OCP_LED OCP_CSW
7Ch TempMon R TI reserved CHIPTEMP_STATUS CHIPTEMP
7Dh Protect R TI reserved
7Eh Version R Version
7Fh Status R ACTTIMER_FAULT ENDDET SIF_TIMEOUTERR PWRERR TSDERR OCPERR TSDFAULT FG
60h Protect R/W TI reserved
61h Protect R/W TI reserved
62h Protect R/W TI reserved
63h SpinAdj R/W TI reserved Mask_Plus TI reserved
64h Protect R/W TI reserved
65h Protect R/W TI reserved
66h Protect R/W TI reserved
6Ch EdetCfg R/W TI reserved STP_WIND_HIZ STP_WIND_H
6Dh DCCfg R/W SWR1_MD_BURST SWR2_MD_BURST SWR1_VOUTUP TI reserved SWR1_BST_HEFF TI reserved
6Eh UtilCfg R/W GPOUT_HL GPOUT_ENA SWROCP_SELCLK TI reserved SWR1_GPIO_CNTL SWR2_GPIO_CNTL
6Fh MonitorSet R/W ACTTIMER_FLT_MON ENDDET_MON SIF_TIMEOUTERR_MON PWRERR_MON TSDERR_MON OCPERR_MON TSDFAULT_MON TI reserved
(1) VTRK and VLOAD is exclusive, using same DAC block

8.6.4 Detailed Description of Register

8.6.4.1 REG01 12-Bit DAC for Tilt

Figure 27. Tilt (REG01) 12-Bit DAC for Tilt (VDAC_MAPSW = 0)
15 14 13 12 11 10 9 8
VTLT
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VTLT
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. Tilt (REG01) Field Descriptions

Bit Field Type Default Description
11-0 VTLT w-0 Digital input code for Tilt.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Output is changed by “differential Tilt mode (REG74[7])”
TLT_OUT = VTLT × (6.0 / 2048) (DIFF_TLT = 0)
TLT_OUT = (VFCS-VTLT) × (6.0 / 2048) (DIFF_TLT = 1)
TLT_OUT should be changed after writing VFCS.
In DIFF_TLT mode (DIFF_TLT = 1), TLT_OUT should be changed after writing VFCS.

8.6.4.2 REG02 12-Bit DAC for Focus

Figure 28. Focus (REG02) 12-Bit DAC for Focus (VDAC_MAPSW = 0)
15 14 13 12 11 10 9 8
VFCS
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VFCS
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. Focus (REG02) Field Descriptions

Bit Field Type Default Description
11-0 VFCS w-0 Digital input code for Focus
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Output is changed by “differential Tilt mode (REG74[7])”
FCS_OUT = VFCS × (6.0 / 2048) (DIFF_TLT = 0)
FCS_OUT = (VFCS – VTLT) × (6.0 / 2048) (DIFF_TLT = 1)

8.6.4.3 REG03 12-Bit DAC for Tracking

Figure 29. Tracking (REG03) 12-Bit DAC for Tracking (VDAC_MAPSW = 0)
15 14 13 12 11 10 9 8
VTRK
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VTRK
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. Tracking (REG03) Field Descriptions

Bit Field Type Default Description
11-0 VTRK w-0 Digital input code for Tracking.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
TRK_OUT = VTRK × (6.0 / 2048)

8.6.4.4 REG04 12-Bit DAC for Sled1

Figure 30. Sled1 (REG04) 10bit DAC for Sled1 (VDAC_MAPSW = 0)
15 14 13 12 11 10 9 8
VSLD1
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VSLD1
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. Sled1 (REG04) Field Descriptions

Bit Field Type Default Description
11-2 VSLD1 w-0 Digital input code for Sled1.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Two bits on LSB, VSLD1[1:0], will be handled with zero.
SLD1_OUT = VSLD1 × (440mA/2048)

8.6.4.5 REG05 12-Bit DAC for Sled2

Figure 31. Sled2 (REG05) 10bit DAC for Sled2 (VDAC_MAPSW = 0)
15 14 13 12 11 10 9 8
VSLD2
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VSLD2
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. Sled2 (REG05) Field Descriptions

Bit Field Type Default Description
11-2 VSLD2 w-0 Digital input code for Sled2.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Two bits on LSB, VSLD2[1:0], will be handled with zero.
SLD2_OUT = VSLD2 × (440mA/2048)

8.6.4.6 REG06 12-Bit DAC for Stepping1

Figure 32. Stepping1 (REG06) 8bit DAC for Stepping1 (VDAC_MAPSW = 0)
15 14 13 12 11 10 9 8
VSTP1
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VSTP1
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. Stepping1 (REG06) Field Descriptions

Bit Field Type Default Description
11-4 VSTP1 w-0 Digital input code for Stepping1.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Four bits on LSB, VSTP1[3:0], will be handled with zero.
VSTP1_OUT = VSTP1 × (5.0/2048) @P5V=5.0V

8.6.4.7 REG07 12-Bit DAC for Stepping2

Figure 33. Stepping2 (REG07) 8bit DAC for Stepping2 (VDAC_MAPSW = 0)
15 14 13 12 11 10 9 8
VSTP2
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VSTP2
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. Stepping2 (REG07) Field Descriptions

Bit Field Type Default Description
11-4 VSTP2 w-0 Digital input code for Stepping1.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Four bits on LSB, VSTP2[3:0], will be handled with zero.
VSTP2_OUT = VSTP2 × (5.0/2048) @P5V=5.0V

8.6.4.8 REG08 12-Bit DAC for Spindle

Figure 34. Spindle (REG08) 12-Bit DAC for Spindle (VDAC_MAPSW = 0)
15 14 13 12 11 10 9 8
VSPM
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VSPM
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. Spindle (REG08) Field Descriptions

Bit Field Type Default Description
11-0 VSPM w-0 Digital input code for Spindle.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
SPM_OUT = VSPM × (6.0 / 2048)

8.6.4.9 REG09 12-Bit DAC for Load

Figure 35. Load (REG09) 12-Bit DAC for Load (VDAC_MAPSW = 0)
15 14 13 12 11 10 9 8
VLOAD
w-0 w-0 w-0 w-0
7 6 5 4 3 2 1 0
VLOAD
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. Load (REG09) Field Descriptions

Bit Field Type Default Description
11-0 VLOAD w-0 Digital input code for Load.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
LOAD_OUT = VLOAD × (6.0 / 2048)

8.6.4.10 REG63 8-Bit Control Register for SpinAdj

Figure 36. SpinAdj (REG63)
7 6 5 4 3 2 1 0
TI reserved Mask_Plus TI reserved
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. SpinAdj (REG63) Field Descriptions

Bit Field Type Default Description
7-2 TI reserved r-0
1 Mask_Plus r-0 0 Mask Plus bit enables fly back robustness by optimizing masking time.
0: Default masking time
1: Extended masking time for large inductance motor
0 TI reserved r-0

8.6.4.11 REG6C 8-Bit Control Register for EDetCfg

Figure 37. EDetCfg (REG6C)
7 6 5 4 3 2 1 0
TI reserved STP_WIND_HIZ STP_WIND_H
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. EDetCfg (REG6C) Field Descriptions

Bit Field Type Default Description
7-2 TI reserved r-0
1 STP_WIND_HIZ r-0 0 0: normal end detection
1: when detecting BEMF, set STP1 and STP2 FET HIZ to reduce mutual noise.
0 STP_WIND_H r-0 0 0: normal end detection
1: when detecting BEMF, set driving phase to Hi ( Detecting phase put Hi-Z ) to reduce mutual noise.

8.6.4.12 REG6D 8-Bit Control Register for DCCfg

Figure 38. DCCfg (REG6D)
7 6 5 4 3 2 1 0
SWR1_MD_BURST SWR2_MD_BURST SWR1_VOUTUP TI reserved SWR1_BST_HEFF TI reserved
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. DCCfg (REG6D) Field Descriptions

Bit Field Type Default Description
7 SWR1_MD_BURST rw-0 0 0: V1Px normal regulation
1: V1Px discontinuous mode
6 SWR2_MD_BURST rw-0 0 0: V3P3 normal regulation
1: V3P3 discontinuous mode
5-4 SWR1_VOUTUP rw-0 0 V1Px DC-DC converter voltage up
For 1.2 V or 1.5 V:
00: 0%
01: 2%
10: 3.6%
11: 5.5%
For 1.0 V:
00: 0%
01: 1.3%
10: 2.4%
11: 3.3%
3 TI reserved rw-0
2 SWR1_BST_HEFF rw-0 0 1: V1Px High efficiency mode on discontinuous mode
This bit will be enabled in SWR1_MD_BURST=1
1-0 TI reserved rw-0

8.6.4.13 REG6E 8-Bit Control Register for UtilCfg

Figure 39. UtilCfg (REG6E)
7 6 5 4 3 2 1 0
GPOUT_HL GPOUT_ENA SWROCP_SELCLK TI reserved SWR1_GPIO_CNTL SWR2_GPIO_CNTL
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 20. UtilCfg (REG6E) Field Descriptions

Bit Field Type Default Description
7 GPOUT_HL rw-0 0 GPOUT (general-purpose output) pin output selection
0: low output
1: high output
valid only REG6F = 00h
6 GPOUT_ENA rw-0 0 Enable monitor signal output to GPOUT pin
0: No signal output, Hi-Z
1: output signal selected in REG6F with CMOS output
Output is Logical OR when selected two more signals
5-4 SWROCP_SELCLK rw-0 0 Over current protection monitoring frequency
5 counts by
00: 5 kHz (= exceed 1 ms)
01: 20 kHz
10: 50 kHz
11: 500 kHz
3-2 TI reserved rw-0
1 SWR1_GPIO_CNTL rw-0 0 Set REG1PX pin as GPIO1 pin.
0: REG1PX pin as 1.xV DC-DC converter output
1: Open drain control for GPOUT1 pin (at V1Px DC-DC disable)
0 SWR2_GPIO_CNTL rw-0 0 Set REG3P3 pin as GPIO2 pin.
0: REG3P3 pin as 3.3V DC-DC converter output
1: Open drain control for GPOUT1 pin (at V1Px DC-DC disable)
Open drain control for GPOUT2 pin (at V3P3 DC-DC disable)

8.6.4.14 REG6F 8-Bit Control Register for MonitorSet

Figure 40. MonitorSet (REG6F)
7 6 5 4 3 2 1 0
ACTTIMER_FLT_MON ENDDET_MON SIF_TIMEOUTERR_MON PWRERR_MON TSDERR_MON OCPERR_MON TSDFAULT_MON TI reserved
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. MonitorSet (REG6F) Field Descriptions

Bit Field Type Default Description
7 ACTTIMER_FLT_MON rw-0 0 1: ACTTIMER fault output to GPOUT pin
6 ENDDET_MON rw-0 0 1: ENDDET monitor output to GPOUT pin
5 SIF_TIMEOUTERR_MON rw-0 0 1: SIF timeout monitor output to GPOUT pin
4 PWRERR_MON rw-0 0 1: PWRERR monitor output to GPOUT pin
3 TSDERR_MON rw-0 0 1: TSDERR fault output to GPOUT pin
2 OCPERR_MON rw-0 0 1: OCPERR fault output to GPOUT pin
1 TSDFAULT_MON rw-0 0 1: TSDFAULT fault output to GPOUT pin

8.6.4.15 REG70 8bit Control Register for DriverEna

Figure 41. REG70 8bit Control Register
7 6 5 4 3 2 1 0
TLT_ENA FCS_ENA TRK_ENA SPM_ENA SLD_ENA STP_ENA LOAD_ENA XSLEEP
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22. DriverEna (REG70) Field Descriptions

Bit Field Type Default Description
7 TLT_ENA rw-0 1 : Tilt enable (with XSLEEP=1)
6 FCS_ENA rw-0 1: Focus enable (with XSLEEP=1)
5 TRK_ENA rw-0 1: Track enable (with XSLEEP=1)
4 SPM_ENA rw-0 1: Spindle enable (with XSLEEP=1)
3 SLD_ENA rw-0 1: Sled enable (with XSLEEP=1)
2 STP_ENA rw-0 1: Step enable (with XSLEEP=1)
1 LOAD_ENA rw-0 1 : LOAD enable (with XSLEEP=1)
Track (bit5:TRK_ENA) will be disabled at LOAD_ENA=1 because of sharing the DAC PWM module. Load priority is higher than TRK_ENA.
0 XSLEEP rw-0 1: Operation mode
0: Power save mode
Charge pump enable bit.
All driver enable bit (Bit[7:1]) change disabled and output change to Hi-Z (regardless of setting xxx_ENA bit is 1 when setting XSLEEP to 0. Therefore set 1 to XSLEEP before setting each enable bits.

8.6.4.16 REG71 8-Bit Control Register for FuncEna

Figure 42. REG71 8-Bit Control Register for FuncEna (REG71)
7 6 5 4 3 2 1 0
SPM_LSMODE ENDDET_ENA ENDDET_SLCT LED_ON CSW_ON TEMPMON_ENA TI reserved
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. FuncEna (REG71) Field Descriptions

Bit Field Type Default Description
7 SPM_LSMODE rw-0 0 : Spindle Normal rotation mode
1 : Light Scribe mode (slow rotation mode)
6 ENDDET_ENA rw-0 1 : use sled/step End detection enable ( with STP_ENA=1 or SLD_ENA=1)
5 ENDDET_SLCT rw-0 0 : Sled End detection monitor
1 : Step End detection monitor
4 LED_ON rw-0 1 : LEDO enable ( with XSLEEP=1)
3 CSW_ON rw-0 1 : CSWO enable ( with XSLEEP=1)
2 TEMPMON_ENA rw-0 1: enable chip temperature monitoring ( with XSLEEP=1)
1-0 TI reserved rw-0 Reserved

8.6.4.17 REG72 8-Bit Control Register for ACTCfg

Figure 43. ACTCfg (REG72)
7 6 5 4 3 2 1 0
LOAD_O5CH_HIGH LOADPROT_OFF ACTPROT_OFF ACTTEMPTH
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. ACTCfg (REG72) Field Descriptions

Bit Field Type Default Description
7 LOAD_05CH_HIGH rw-0 0 LOAD output polarity at 0.5CH ( REG74h[6]=1 )
0: LOADP=Low
1: LOADP=High
6 LOADPROT_OFF rw-0 0 1: Load Over Current Protection OFF
5 ACTPROT_OFF rw-0 0 0 : Actuator protection ON
1 : Actuator Fault monitor disable (No protection for ACT channel)
4-0 ACTTEMPTH rw-0 0 Actuator thermal protection (=ACT Timer) threshold level
ACT Timer Protection enable except ACTTEMPTH[4:0] = 0x00
ACTTEMPTH = 0x00 equal to ACTPROT_OFF = 1
By writing value 0x00, ACTTIMER_PROT flag is cleared.

8.6.4.18 REG73 8-Bit Control Register for Parm0

Figure 44. Parm0 (REG73)
7 6 5 4 3 2 1 0
SIF_TIMEOUT_TH SLEDEND_HZTIME SLDENDTH STPEND_HZTIME STPENDTH
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. Parm0 (REG73) Field Descriptions

Bit Field Type Default Description
7-6 SIF_TIMEOUT_TH rw-0 0 Watch dog timer for Serial communication
0: disable 1: 1 ms 2: 100 µs 3: 10 µs
Set SIF_TIMEOUTERR (REG7F) if communication is suspended for this time period. XRESET processing will be performed if a SIF_TIMEOUTERR occurs.
5 SLEDEND_HZTIME rw-0 0 Time window for sled end detection.
0: 400 µs 1: 200 µs
Caution) Need to recycle ENDDET_ENA = 0 → 1 after writing this bit.
4-3 SLDENDTH rw-0 0 Sled end detection sensibility setting. Detection threshold for motor BEMF
00: 46 mV 01: 86 mV 10: 0 mV 11: 22 mV
2 STPEND_HZTIME rw-0 0 Step High-Z detection period in End detection
0: 400 µs 1: 200 µs
Caution) Need to recycle ENDDET_ENA = 0 → 1 after writing this bit.
1-0 STPENDTH rw-0 0 Step end detection sensibility setting
00: 39 mV 01: 60 mV 10: 0 mV 11: 19 mV

8.6.4.19 REG74 8-Bit Control Register for SIFCfg

Figure 45. SIFCfg (REG74)
7 6 5 4 3 2 1 0
DIFF_TLT LOAD_05CH RDSTAT_ON_VFCS VSLD2_POL VSTP2_POL ADVANCE_RD SOMI_HIZ VDAC_MAPSW
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 26. SIFCfg (REG74) Field Descriptions

Bit Field Type Default Description
7 DIFF_TLT rw-0 0 1 : Differential Tilt mode enable (with TLT_ENA=FCS_ENA=1)
Differential Tilt mode (DIFF_TLT=1), DAC value setting as follows
FCS_OUT=(VFCS+VTLT) × 6/2048
TLT_OUT=(VFCS-VTLT) × 6/2048
In DIFF_TLT mode (DIFF_TLT=1), TLT_OUT should be changed after writing VFCS.
6 LOAD_05CH rw-0 0 The setting of Load motor driving type. Load output changes as follow
0: 1ch mode (LOAD output is controlled by DAC code, VLOAD)
Use for Slot-in model or 1ch tray model.
1: 0.5Ch mode (LOAD is only controlled by LOAD_05CH_HIGH)
Use for Tray model
5 RDSTAT_ON_VFCS rw-0 0 Set Read status data (REG7F) at VFCS write command (REG02)
1: enable Write and Read mode
(Write 12bits Focus DAC data + Read 8bits status data)
4 VSLD2_POL rw-0 0 change direction of SLED rotation
3 VSTP2_POL rw-0 0 change direction of STEP rotation
2 ADVANCE_RD rw-0 0 Advanced serial read timing
1: Read back timing changes half clock advance.
1 SOMI_HIZ rw-0 0 0: SOMI line High-Z at bus idling time.
1: SOMI line Pull Down at bus idling time.
0 VDAC_MAPSW rw-0 0 1: change channel assignments of DAC register (REG01~09)

8.6.4.20 REG76 8-Bit Control Register for WriteEna

Figure 46. WriteEna (REG76)
7 6 5 4 3 2 1 0
WRITE_ENABLE TI reserved REG6X_WR
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27. WriteEna (REG76) Field Descriptions

Bit Field Type Default Description
7 WRITE_ENABLE rw-0 0 0: Register Write disable except REG76
1: Write enable for registers REG01~0B, REG70~7F
6-1 TI reserved rw-0
0 REG6X_WR rw-0 0 0: Register REG63 write disable
1: Register REG63 write enable

8.6.4.21 REG77 8-Bit Control Register for ClrReg

Figure 47. ClrReg (REG77)
7 6 5 4 3 2 1 0
RST_INDAC RST_REGS RST_ERR_FLAG RST_REGS_WO3 TI reserved
w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. ClrReg (REG77) Field Descriptions

Bit Field Type Default Description
7 RST_INDAC w-0 0 1 : Reset all 12bit input DAC register (REG01~0B)
*Self clear bit
6 RST_REGS w-0 0 1 : Reset all 8bit R/W Registers (REG70h~77h, 60h-6Fh)
*Self clear bit
5 RST_ERR_FLAG w-0 0 1 : Reset Fault Flag Latch (REG7F[5:1], REG79~REG7B)
*Self clear bit
4 RST_REGS_WO3 w-0 0 1 : Reset all 8bit R/W Registers w/o XSLEEP, CSW_ON, LED_ON (REG70h~76h, REG60h~66h)
*Self clear bit
3-0 TI reserved w-0

8.6.4.22 REG78 8-Bit Control Register for ActTemp

Figure 48. ActTemp (REG78)
7 6 5 4 3 2 1 0
TI reserved ACT_TIMER_PROT ACTTEMP
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. ActTemp (REG78) Field Descriptions

Bit Field Type Default Description
7-6 TI reserved r-0
5 ACT_TIMER_PROT r-0 0 ACT timer protection flag
1: ACT Timer Protection has detected and latched.
(ACTTEMP > ACTTEMPTH)
This bit holds data after temperature change to low since this is a latch bit. Also driver output keep Hi-Z until setting RST_ERR_FLAG or ACTTEMPTH = 0.
4-0 ACTTEMP r-0 0 An integrated value of ACT_TIMER counters at present.

8.6.4.23 REG79 8-Bit Control Register for UVLOMon

Figure 49. UVLOMon (REG79)
7 6 5 4 3 2 1 0
TI reserved UVLO_A5V UVLO_INT3P3 UVLO_SWR3P3 UVLO_SWR1PX OVP_P5V
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 30. UVLOMon (REG79) Field Descriptions

Bit Field Type Default Description
7-5 TI reserved r-0
4 UVLO_A5V r-0 0 UVLO flag for detection Low A5V supply(1)
3 UVLO_INT3P3 r-0 0 UVLO flag for detection Low internal 3.3V regulator(1)
2 UVLO_SWR3P3 r-0 0 UVLO flag for detection Low DC-DC 3.3V (1)
1 UVLO_SWR1PX r-0 0 UVLO flag for detection Low DC-DC 1.xV (1)
0 OVP_P5V r-0 0 Over voltage protection flag for P5Vsply (1)
(1) Latched first reset event only. Cleared by “RST_ERR_FLG” (REG77)

8.6.4.24 REG7A 8-Bit Control Register for ThPMon

Figure 50. ThPMon (REG7A)
7 6 5 4 3 2 1 0
TSD_FAULT_SWR TSD_FAULT_SPM TSD_FAULT_ACT TSD_FAULT_LEDCSW TSD_SWR TSD_SPM TSD_ACT TSD_ LEDCSW
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 31. ThPMon (REG7A) Field Descriptions

Bit Field Type Default Description
7 TSD_FAULT_SWR r-0 0 Pre alert of thermal protection for DC-DC converter block*.
6 TSD_FAULT_SPM r-0 0 Pre alert of thermal protection of Spindle block*
5 TSD_FAULT_ACT r-0 0 Pre alert of thermal protection of Focus /Track /Tilt Sled1 /Sled2 /Step1 /Step2 /Load *
4 TSD_FAULT_LEDCSW r-0 0 Pre alert of thermal protection of CSW/LED *
3 TSD_SWR r-0 0 Thermal protection flag for DC-DC converter block *
DC-DC converter output Hi-Z until temperature falls on release level
1: detect (latch)
2 TSD_SPM r-0 0 Thermal protection flag for Spindle *
SPM output Hi-Z until temperature falls on release level
1: detect (latch)
1 TSD_ACT r-0 0 Thermal protection flag for Focus /Track /Tilt Sled1 /Sled2 /Step1 /Step2 /Load *
Actuator output Hi-Z until temperature falls on release level
1: detect (latch)
0 TSD_ LEDCSW r-0 0 Thermal protection flag for CSW/LED *
LED/CSW output Hi-Z until temperature falls on release level
1: detect (latch)

8.6.4.25 REG7B 8-Bit Control Register for OCPMon

Figure 51. OCPMon (REG7B)
7 6 5 4 3 2 1 0
TI reserved OCP_SWR OCP_STP OCP_LOAD OCP_LED OCP_CSW
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 32. OCPMon (REG7B) Field Descriptions

Bit Field Type Default Description
7-5 TI reserved r-0
4 OCP_SWR r-0 0 Over current protection flag bit for DC-DC converter block. (1)
3 OCP_STP r-0 0 Over current protection flag bit for step block. (1)
2 OCP_LOAD r-0 0 Over current protection flag bit for Load block. (1)
1 OCP_LED r-0 0 Over current protection flag bit for LED block. (1)
0 OCP_CSW r-0 0 Over current protection flag bit for CSW block. (1)
(1) Cleared by “RST_ERR_FLAG” bit (REG77)

8.6.4.26 REG7C 8-Bit Control Register for TempMon

Figure 52. TempMon (REG7C)
7 6 5 4 3 2 1 0
TI reserved CHIPTEMP_STATUS CHIPTEMP
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 33. TempMon (REG7C) Field Descriptions

Bit Field Type Default Description
7 TI reserved r-0
6 CHIPTEMP_STATUS r-0 0 1: New data CHIPTEMP[5:0] is updated
It will be cleared after reading.
5-0 CHIPTEMP r-0 0 Chip temperature monitor (2.5deg/LSB)
15(0) to 172.5(63) degrees.
For monitoring, TEMPMON_ENA=1 and XSLEEP=1 is required

8.6.4.27 REG7E 8-Bit Control Register for Version (REG7E)

Figure 53. Version (REG7E)
7 6 5 4 3 2 1 0
Version
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 34. Version (REG7E) Field Descriptions

Bit Field Type Default Description
7-0 Version r-0 Version[7:4] = revision number of TPIC2010
Version[3:0]=option

8.6.4.28 REG7F 8-Bit Control Register for Status (REG7F)

Figure 54. Status (REG7F)
7 6 5 4 3 2 1 0
ACTTIMER_FAULT ENDDET SIF_TIMEOUTERR PWRERR TSDERR OCPERR TSDFAULT FG
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 35. Status (REG7F) Field Descriptions

Bit Field Type Default Description
7 ACTTIMER_FAULT r-0 0 Status flag of ACTTIMER protection
1: Pre alert of ACTTIMER protection. It is close to the threshold level. You can get current ACTTIMER value in REG78.
Both of this bit and ACT_TIMER_PROT (REG78) will be set when over the threshold.
6 ENDDET r-0 0 status flag of END detection
1: end position detected (not latch bit)
5 SIF_TIMEOUTERR r-0 0 error flag of serial I/F watch dog timer
1: SIF communication was interrupted, expired watch dog timer
4 PWRERR r-0 0 error flag of Power
1 : Voltage problem occurred, details in REG79
3 TSDERR r-0 0 error flag of any over thermal protections
1: Dispatched thermal protection, details in REG7A
2 OCPERR r-0 0 error flag of any over current protection
1: Dispatched OCP, details in REG7Bh
1 TSDFAULT r-0 0 warning of TSD of any thermal protection
1 : Detect pre thermal protection details in REG7A
0 FG r-0 0 FG signal. Spindle rotation pulse for speed monitor