SLVSAX6H October   2011  – December 2015 TPS2002C , TPS2003C , TPS2052C , TPS2060C , TPS2062C , TPS2062C-2 , TPS2064C , TPS2064C-2 , TPS2066C , TPS2066C-2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: TJ = TA = 25°C
    6. 7.6 Electrical Characteristics: -40°C ≤ (TJ = TA) ≤ 125°C
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Undervoltage Lockout (UVLO)
      2. 9.3.2 Enable (ENx or ENx)
      3. 9.3.3 Deglitched Fault Reporting
      4. 9.3.4 Overcurrent Protection
      5. 9.3.5 Overtemperature Protection
      6. 9.3.6 Softstart, Reverse Blocking and Discharge Output
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Input and Output Capacitance
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Self-Powered and Bus-Powered Hubs
    2. 11.2 Low-Power Bus-Powered and High-Power Bus-Powered Functions
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Power Dissipation and Junction Temperature
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN MAX UNIT
Voltage range on IN, OUTx, ENx or ENx, FLTx(4) –0.3 6 V
Voltage range from IN to OUT –6 6 V
Maximum junction temperature, TJ Internally limited °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Absolute maximum ratings apply over recommended junction temperature range.
(3) All voltages are with respect to GND unless otherwise noted.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
IEC 61000-4-2, contact discharge(3) ±8000 V
IEC 61000-4-2, air-gap discharge(3) ±15000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) VOUT was surged on a PCB with input and output bypassing per Figure 22 (except input capacitor was 22 µF) with no device failure.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage, IN 4.5 5.5 V
VEnable Input voltage, ENx or ENx 0 5.5
IOUTx Continuous output current, OUTx TPS2052C 0.5 A
TPS2062C, TPS2062C-2, TPS2066C,
and TPS2066C-2		 1
TPS2060C, TPS2064C, and TPS2064C-2 1.5
TPS2002C and TPS2003C 2
TJ Operating junction temperature –40 125 °C
IFLTx Sink current into FLTx 0 5 mA

7.4 Thermal Information

THERMAL METRIC(1)(2) TPS2052C
TPS2062C
TPS2066C
TPS2066C-2
TPS2060C
TPS2064C
TPS2064C-2		 TPS2062C
TPS2066C		 TPS2062C-2 TPS2002C
TPS2003C		 UNIT
DGN (MSOP) D (SOIC) DRB (SON) DRC (VSON)
8 PINS 8 PINS 8 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 57.2 129.9 50.8 45.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 110.5 83.5 60.3 58 °C/W
RθJB Junction-to-board thermal resistance 60.7 70.4 26.3 21.1 °C/W
ψJT Junction-to-top characterization parameter 7.8 36.6 2.1 1.9 °C/W
ψJB Junction-to-board characterization parameter 24 66.9 26.5 21.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 14.3 n/a 9.8 9.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

7.5 Electrical Characteristics: TJ = TA = 25°C

VIN = 5 V, VENx = VIN or VENx = 0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
POWER SWITCH
rDS(on) On-resistance TPS2052C (0.5 A) DGN 70 84 mΩ
TPS2052C (0.5 A)
–40°C ≤ (TJ, TA) ≤ 85°C		 DGN 70 95
TPS2062C, 66C, and 66C-2 (1 A) DGN 70 84
TPS2062C, 66C, and 66C-2 (1 A),
–40°C ≤ (TJ, TA) ≤ 85°C		 DGN 70 95
TPS2062C and 66C (1 A) D 90 108
TPS2062C and 66C (1 A)
–40°C ≤ (TJ, TA) ≤ 85°C		 D 90 122
TPS2062C-2 (1 A) DRB 73 87
TPS2062C-2 (1 A)
–40°C ≤ (TJ, TA) ≤ 85°C		 DRB 73 101
TPS2060C, 64C, and 64C-2 (1.5 A) 70 84
TPS2060C, 64C, and 64C-2 (1.5 A)
–40°C ≤ (TJ, TA) ≤ 85°C		 70 95
TPS2002C and 03C (2 A) 70 84
TPS2002C and 03C (2 A)
–40°C ≤ (TJ, TA) ≤ 85°C		 70 95
CURRENT LIMIT
IOS Current-limit (see Figure 28) TPS2052C (0.5 A) 0.75 1 1.25 A
TPS2062C, 62C-2, 66C, and 66C-2 (1 A) 1.28 1.61 1.94
TPS2060C, 64C, and 64C-2 (1.5 A) 1.83 2.29 2.75
TPS2002C and 03C (2 A) 2.55 3.15 3.77
SUPPLY CURRENT
ISD Supply current, switch disabled I(OUTx) = 0 mA 0.01 1 µA
IS1E Supply current, single switch enabled I(OUTx) = 0 mA 60 75
IS2E Supply current, both switches enabled I(OUTx) = 0 mA 100 120
ILKG Leakage current VOUT = 0 V, VIN = 5.5 V, disabled,
measured IVIN 		TPS20xxC-2 0.05 1
Reverse leakage current VOUT = 5.5 V, VIN = 0 V, measured I(OUTx) 0.15 1
OUTPUT DISCHARGE
RPD Output pulldown resistance(2) VIN = VOUTx = 5 V, disabled TPS20xxC 400 470 600 Ω
(1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
(2) These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s product warranty.

7.6 Electrical Characteristics: –40°C ≤ (TJ = TA) ≤ 125°C(1)

4.5 V ≤ VIN ≤ 5.5 V, VENx = VIN or VENx = 0 V, IOUTx = 0 A (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) MIN TYP(3) MAX UNIT
POWER SWITCH
rDS(on) On-resistance TPS2052C (0.5 A) DGN 70 112 mΩ
TPS2062C, 66C, and 66C-2 (1 A) DGN 70 112
TPS2062C and 66C (1 A) D 90 135
TPS2062C-2 (1 A) DRB 73 115
TPS2060C, 64C, and 64C-2 (1.5 A) DGN 70 112
TPS2002C and 03C (2 A) DRC 70 112
ENABLE INPUT (ENx or ENx)
VIH ENx (ENx), High-level input voltage 4.5 V ≤ VIN ≤ 5.5 V 2 V
VIL ENx (ENx), Low-level input Voltage 0.8
Hysteresis VIN = 5 V 0.14
Leakage current VENx = 5.5 V or 0 V, VENx = 0 V or 5.5 V –1 0 1 µA
ton Turnon time (2) VIN = 5 V, CL = 1 µF, RL = 100 Ω, ENx ↑ or ENx ↓
(see Figure 25, Figure 26, and Figure 23)
1 A, 1.5 A, 2 A Rated		 1.4 1.9 2.4 ms
toff Turnoff time (2) VIN = 5 V, CL = 1 µF, RL = 100 Ω, ENx ↑ or EN ↓
(see Figure 25, Figure 26, and Figure 23)
1 A, 1.5 A, 2 A Rated		 1.95 2.60 3.25 ms
tr Rise time, output (2) CL = 1 µF, RL = 100 Ω (see Figure 24)
1 A, 1.5 A, 2 A Rated		 0.58 0.82 1.15 ms
tf Fall time, output (2) CL = 1 µF, RL = 100 Ω (see Figure 24)
1 A, 1.5 A, 2 A Rated		 0.33 0.47 0.66 ms
CURRENT LIMIT
IOS Current-limit (see Figure 28) TPS2052C (0.5 A) 0.7 1 1.3 A
TPS2062C, 62C-2, 66C, and 66C-2 (1 A) 1.12 1.61 2.10
TPS2060C, 64C, and 64C-2 (1.5 A) 1.72 2.29 2.86
TPS2002C and 03C (2 A) 2.35 3.15 3.95
tIOS Short-circuit response time VIN = 5 V (see Figure 27),
One-half full load → R(SHORT) = 50 mΩ, Measure from application to when current falls below 120% of final value		 2 µs
SUPPLY CURRENT
ISD Supply current, switch disabled Standard conditions, I(OUTx) = 0 mA 0.01 10 µA
IS1E Supply current, single switch enabled Standard conditions, I(OUTx) = 0 mA 90
IS2E Supply current, both switches enabled Standard conditions, I(OUTx) = 0 mA 150
ILKG Leakage current VOUT = 0 V, VIN = 5.5 V, disabled,
measured IVIN 		TPS20xxC-2 0.05
Reverse leakage current VOUT = 5.5 V, VIN = 0 V, measured I(OUTx) 0.20
UNDERVOLTAGE LOCKOUT
UVLO Low-level input voltage, IN VIN rising 3.4 4.0 V
Hysteresis, IN 0.14 V
FLTx
Output low voltage, FLTx I(FLTx) = 1 mA 0.2 V
Off-state leakage V(FLTx) = 5.5 V 1 µA
FLTx deglitch (2) FLTx overcurrent assertion and deassertion 7 10 13 ms
OUTPUT DISCHARGE
Output pulldown resistance(2) VIN = 5 V, VOUT = 5 V, disabled TPS20xxC 300 470 800 Ω
VIN = 4 V, VOUT = 5 V, disabled TPS20xxC 350 560 1200
THERMAL SHUTDOWN
Junction thermal shutdown threshold In current limit 135 °C
Not in current limit 155
Hysteresis 20 °C
(1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature.
(2) These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s product warranty.
(3) Typical values are at 5 V and 25°C.

7.7 Typical Characteristics

TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2062C_turnon_delay_rise_time_lvsax6.png
Figure 1. TPS2062C Turnon Delay and
Rise Time With 1-μF Load
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2062C_turnon_delay_rise_time_150uF_lvsax6.png
Figure 3. TPS2062C Turnon Delay and
Rise Time With 150-μF Load
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2062C_enable_into_short_lvsax6.png
Figure 5. TPS2062C Enable Into Short
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2062C_PowerUp_enabled_lvsax6.png
Figure 7. TPS2062C Power Up – Enabled
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2062C_enable_with_2load_lvsax6.gif
Figure 9. TPS2062C Enable With 2-Ω Load
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2062C_enable_disable_into_short_lvsax6.gif
Figure 11. TPS2062C Enable and Disable
into Output Short
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2064C_enable-into_short_lvsax6.gif
Figure 13. TPS2064C Enable into Short
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2064C_hot_short_lvsax6.gif
Figure 15. TPS2064C Short Applied
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2003C_Turn_on_lvsax6.gif
Figure 17. TPS2003C Enable into 2.5 Ω and 150-μF Load
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C Rdson_vs_temperature_lvsax6.gif
Figure 19. Input - output Resistance (RDS(ON))
vs Temperature
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C Ise_vs_temperature_lvsax6.gif
Figure 21. Supply Current (Enable) - ISE vs Temperature
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2062C_turnoff_delay_fall_time_1uF_lvsax6.png
Figure 2. TPS2062C Turnoff Delay and
Fall Time With 1-μF Load
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2062C_turnoff_delay_fall_time_150uF_lvsax6.png
Figure 4. TPS2062C Turnoff Delay and
Fall Time With 150-μF Load
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2062C_inrush_curren_ with_different_load cap_lvsax6.png
Figure 6. TPS2062C In-rush Current
With Different Load Capacitance
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2062C_power_down_lvsax6.png
Figure 8. TPS2062C Power Down – Enabled
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2062C_Enable_with_1.0Load_lvsax6..png
Figure 10. TPS2062C Enable With 1-Ω Load
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2062C_enable_disable_into10_lvsax6.gif
Figure 12. TPS2062C Enable and Disable
into 10-Ω Load
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2064C_enable_into_full_load_150uF_lvsax6.png
Figure 14. TPS2064C Enable into 3.3 Ω and 150-μF Laod
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C TPS2003_enable_into_short_lvsax6.gif
Figure 16. TPS2003C Enable into Short
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C Ios_VS_temperature_lvsax6.png
Figure 18. Current Limit (IOS) vs Temperature
TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C Isd_vs_temperature_lvsax6.gif
Figure 20. Supply Current (Device Disable) - ISD
vs Temperature