SLUSC25A February   2015  – August 2017 TPS2388

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2. 5.1 Detailed Pin Description
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Timing Diagrams
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Port Remapping
      2. 8.3.2 Port Power Priority
      3. 8.3.3 A/D Converter
      4. 8.3.4 I2C Watchdog
      5. 8.3.5 Foldback Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Port Operating Modes
        1. 8.4.1.1 Semiauto
        2. 8.4.1.2 Manual
        3. 8.4.1.3 Power Off
      2. 8.4.2 Detection
      3. 8.4.3 Classification
      4. 8.4.4 DC Disconnect
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1  Complete Register Set
      2. 8.6.2  INTERRUPT Register
        1. Table 4. INTERRUPT Register Field Descriptions
      3. 8.6.3  INTERRUPT MASK Register
        1. Table 5. INTERRUPT MASK Register Field Descriptions
      4. 8.6.4  POWER EVENT Register
        1. Table 6. POWER EVENT Register Field Descriptions
      5. 8.6.5  DETECTION EVENT Register
        1. Table 7. DETECTION EVENT Register Field Descriptions
      6. 8.6.6  FAULT EVENT Register
        1. Table 8. FAULT EVENT Register Field Descriptions
      7. 8.6.7  START/ILIM EVENT Register
        1. Table 9. START/ILIM EVENT Register Field Descriptions
      8. 8.6.8  SUPPLY EVENT Register
        1. Table 10. SUPPLY EVENT Register Field Descriptions
      9. 8.6.9  PORT 1 STATUS Register
      10. 8.6.10 PORT 2 STATUS Register
      11. 8.6.11 PORT 3 STATUS Register
      12. 8.6.12 PORT 4 STATUS Register
        1. Table 11. PORT STATUS Register Field Descriptions
      13. 8.6.13 POWER STATUS Register
        1. Table 12. POWER STATUS Register Field Descriptions
      14. 8.6.14 Pin Status Register
        1. Table 13. Pin Status Register Field Descriptions
      15. 8.6.15 OPERATING MODE Register
        1. Table 14. OPERATING MODE Register Field Descriptions
      16. 8.6.16 DISCONNECT ENABLE Register
        1. Table 15. DISCONNECT ENABLE Register Field Descriptions
      17. 8.6.17 DETECT/CLASS ENABLE Register
        1. Table 16. DETECT/CLASS ENABLE Register Field Descriptions
      18. 8.6.18 Port Power Priority/ICUT Disable Register Name
        1. Table 17. Port Power Priority/ICUT Disable Register Field Descriptions
      19. 8.6.19 TIMING CONFIGURATION Register
        1. Table 18. TIMING CONFIGURATION Register Field Descriptions
      20. 8.6.20 GENERAL MASK Register
        1. Table 19. GENERAL MASK Register Field Descriptions
      21. 8.6.21 DETECT/CLASS RESTART Register
        1. Table 20. DETECT/CLASS RESTART Register Field Descriptions
      22. 8.6.22 POWER ENABLE Register
        1. Table 21. POWER ENABLE Register Field Descriptions
      23. 8.6.23 RESET Register
        1. Table 22. RESET Register Field Descriptions
      24. 8.6.24 ID Register
        1. Table 23. ID Register Field Descriptions
      25. 8.6.25 Police 21 Configuration Register
      26. 8.6.26 Police 43 Configuration Register
        1. Table 24. Police 43 Register Field Descriptions
      27. 8.6.27 IEEE Power Enable Register
        1. Table 25. IEEE Power Enable Register Field Descriptions
      28. 8.6.28 Power-on Fault Register
        1. Table 26. Power-on Fault Register Field Descriptions
      29. 8.6.29 PORT RE-MAPPING Register
        1. Table 27. PORT RE-MAPPING Register Field Descriptions
      30. 8.6.30 Port 21 Multi Bit Priority Register
      31. 8.6.31 Port 43 Multi Bit Priority Register
        1. Table 28. Port 43 Register Field Descriptions
      32. 8.6.32 TEMPERATURE Register
        1. Table 29. TEMPERATURE Register Field Descriptions
      33. 8.6.33 INPUT VOLTAGE Register
        1. Table 30. INPUT VOLTAGE Register Field Descriptions
      34. 8.6.34 PORT 1 CURRENT Register
      35. 8.6.35 PORT 2 CURRENT Register
      36. 8.6.36 PORT 3 CURRENT Register
      37. 8.6.37 PORT 4 CURRENT Register
        1. Table 31. PORT 4 CURRENT Register Field Descriptions
      38. 8.6.38 PORT 1 VOLTAGE Register
      39. 8.6.39 PORT 2 VOLTAGE Register
      40. 8.6.40 PORT 3 VOLTAGE Register
      41. 8.6.41 PORT 4 VOLTAGE Register
        1. Table 32. PORT 4 VOLTAGE Register Field Descriptions
      42. 8.6.42 PoE Plus Register
        1. Table 33. PoE Plus Register Field Descriptions
      43. 8.6.43 FIRMWARE REVISION
        1. Table 34. FIRMWARE REVISION Register Field Descriptions
      44. 8.6.44 I2C WATCHDOG Register
        1. Table 35. I2C WATCHDOG Register Field Descriptions
      45. 8.6.45 DEVICE ID Register
        1. Table 36. DEVICE ID Register Field Descriptions
      46. 8.6.46 PORT 1 DETECT RESISTANCE Register
      47. 8.6.47 PORT 2 DETECT RESISTANCE Register
      48. 8.6.48 PORT 3 DETECT RESISTANCE Register
      49. 8.6.49 PORT 4 DETECT RESISTANCE Register
        1. Table 37. PORT 4 DETECT RESISTANCE Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Introduction to PoE
      2. 9.1.2 TPS2388 Application
      3. 9.1.3 Kelvin Current Sensing Resistor
      4. 9.1.4 Connections on Unused Ports
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Pin Bypass Capacitors
        2. 9.2.2.2 Per Port Components
        3. 9.2.2.3 System Level Components (not shown in the schematic diagrams)
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VPWR
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Port Current Kelvin Sensing
    2. 11.2 Layout Example
      1. 11.2.1 Component Placement and Routing Guidelines
        1. 11.2.1.1 Power Pin Bypass Capacitors
        2. 11.2.1.2 Per-Port Components
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.19 TIMING CONFIGURATION Register

COMMAND = 16h with 1 Data Byte, Read/Write

Bit Descriptions: These bits define the timing configuration for all four ports.

Note: the PGn and PEn bits (Power Status register) are cleared when there is a TLIM, TOVLD, TMPDO, or TSTART fault condition.

Figure 38. TIMING CONFIGURATION Register Format
7 6 5 4 3 2 1 0
TLIM TSTART TOVLD TMPDO
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. TIMING CONFIGURATION Register Field Descriptions

BitFieldTypeResetDescription
7 –6 TLIM R/W 0 ILIM fault timing, which is the output current limit time duration before port turn off.

This timer is active and increments to the settings defined below after expiration of the TSTART time window and when the port is limiting its output current to ILIM. If the ILIM counter is allowed to reach the programmed time-out duration specified below, the port will be powered off. The 1-second cool down timer is then started, and the port can not be turned-on until the counter has reached completion.

In other circumstances (ILIM time-out has not been reached), while the port current is below ILIM, the same counter decrements at a rate 1/16th of the increment rate. The counter does not decrement below zero. The ILIM counter is also cleared in the event of a port turn off due to a Power Enable or Port Reset command, a DC disconnect event or the OSS input.

Note that in the event the TLIM setting is changed while this timer is already active for a port, this timer is automatically reset then restarted with the new programmed time-out duration.

Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically restarted if the detect enable bit is set. Also note that the cool down time count is immediately canceled with a port reset command, or if the OFF or Manual mode is selected.

When a PoEPn bit in PoE Plus register is deasserted, the tLIM used for the associated port is always the nominal value (about 60 ms).

If PoEPn bit is asserted, then tLIM for associated port is programmable with the following selection:

TLIM Nominal tLIM (ms)
0 0 60
0 1 15
1 0 12
1 1 10
5-4 TSTART

(or TINRUSH)

 R/W 0 START fault timing, which is the maximum allowed overcurrent time during inrush. If at the end of TSTART period the current is still limited to IInrush, the port is powered off.

This is followed by a 1-second cool down period, during which the port can not be turned-on

Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically restarted if the class and detect enable bits are set.

Note that in the event the TSTART setting is changed while this timer is already active for a port, this new setting is ignored and will be applied only next time the port is turned ON.

The selection is as following:
TSTART Nominal tSTART (ms)
0 0 60
0 1 30
1 0 120
1 1 Reserved
3–2 TOVLD R/W 0 ICUT fault timing, which is the overcurrent time duration before port turn off. This timer is active and increments to the settings defined below after expiration of the TSTART time window and when the port current meets or exceeds ICUT, or when it is limited by the current foldback. If the ICUT counter is allowed to reach the programmed time-out duration specified below, the port will be powered off. The 1-second cool down timer is then started, and the port can not be turned-on until the counter has reached completion.

In other circumstances (ICUT time-out has not been reached), while the port current is below ICUT, the same counter decrements at a rate 1/16th of the increment rate. The counter does not decrement below zero. The ICUT counter is also cleared in the event of a port turn off due to a Power Enable or Port Reset command, a DC disconnect event or the OSS input

Note that in the event the TOVLD setting is changed while this timer is already active for a port, this timer is automatically reset then restarted with the new programmed time-out duration.

Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically restarted if the detect enable bit is set. Also note that the cool down time count is immediately canceled with a port reset command, or if the OFF or Manual mode is selected.

Note that if a DCUTn bit is high in the Port Power Priority/ICUT Disable register, the ICUT fault timing for the associated port is disabled. This means that this port will not be turned off if there is only ICUT fault.

The selection is as following:

TOVLD Nominal tOVLD (ms)
0 0 60
0 1 30
1 0 120
1 1 240
1–0 TMPDO R/W 0 Disconnect delay, which is the time to turn off a port once there is a disconnect condition, and if the dc disconnect detect method has been enabled.

The TDIS counter is reset each time the current goes continuously higher than the disconnect threshold for nominally 15 ms.

The counter does not decrement below zero.

The selection is as following:

TMPDO Nominal tMPDO (ms)
0 0 360
0 1 90
1 0 180
1 1 720