SLVSG51A April   2021  – February 2022 TPS23882B

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1. 6.1 Detailed Pin Description
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Operating Modes
        1. 9.1.1.1 Auto
        2. 9.1.1.2 Autonomous
        3. 9.1.1.3 Semiauto
        4. 9.1.1.4 Manual and Diagnostic
        5. 9.1.1.5 Power Off
      2. 9.1.2 PoE Compliance Terminology
      3. 9.1.3 PoE 2 Type-3 2-Pair PoE
      4. 9.1.4 Requested Class Versus Assigned Class
      5. 9.1.5 Power Allocation and Power Demotion
      6. 9.1.6 Programmable SRAM
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Port Remapping
      2. 9.3.2 Port Power Priority
      3. 9.3.3 Analog-to-Digital Converters (ADC)
      4. 9.3.4 I2C Watchdog
      5. 9.3.5 Current Foldback Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Detection
      2. 9.4.2 Classification
      3. 9.4.3 DC Disconnect
    5. 9.5 I2C Programming
      1. 9.5.1 I2C Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Complete Register Set
      2. 9.6.2 Detailed Register Descriptions
        1. 9.6.2.1  INTERRUPT Register
        2. 9.6.2.2  INTERRUPT MASK Register
        3. 9.6.2.3  POWER EVENT Register
        4. 9.6.2.4  DETECTION EVENT Register
        5. 9.6.2.5  FAULT EVENT Register
        6. 9.6.2.6  START/ILIM EVENT Register
        7. 9.6.2.7  SUPPLY and FAULT EVENT Register
          1. 9.6.2.7.1 Detected SRAM Faults and "Safe Mode"
        8. 9.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 9.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 9.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 9.6.2.11 CHANNEL 4 DISCOVERY Register
        12. 9.6.2.12 POWER STATUS Register
        13. 9.6.2.13 PIN STATUS Register
          1. 9.6.2.13.1 AUTONOMOUS MODE
        14. 9.6.2.14 OPERATING MODE Register
        15. 9.6.2.15 DISCONNECT ENABLE Register
        16. 9.6.2.16 DETECT/CLASS ENABLE Register
        17. 9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
        18. 9.6.2.18 TIMING CONFIGURATION Register
        19. 9.6.2.19 GENERAL MASK Register
        20. 9.6.2.20 DETECT/CLASS RESTART Register
        21. 9.6.2.21 POWER ENABLE Register
        22. 9.6.2.22 RESET Register
        23. 9.6.2.23 ID Register
        24. 9.6.2.24 Connection Check and Auto Class Status Register
        25. 9.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 9.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 9.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 9.6.2.28 2-Pair Police Ch-4 Configuration Register
        29. 9.6.2.29 Capacitance (Legacy PD) Detection
        30. 9.6.2.30 Power-on Fault Register
        31. 9.6.2.31 PORT RE-MAPPING Register
        32. 9.6.2.32 Channels 1 and 2 Multi Bit Priority Register
        33. 9.6.2.33 Channels 3 and 4 Multi Bit Priority Register
        34. 9.6.2.34 Port Power Allocation Register
        35. 9.6.2.35 TEMPERATURE Register
        36. 9.6.2.36 INPUT VOLTAGE Register
        37. 9.6.2.37 CHANNEL 1 CURRENT Register
        38. 9.6.2.38 CHANNEL 2 CURRENT Register
        39. 9.6.2.39 CHANNEL 3 CURRENT Register
        40. 9.6.2.40 CHANNEL 4 CURRENT Register
        41. 9.6.2.41 CHANNEL 1 VOLTAGE Register
        42. 9.6.2.42 CHANNEL 2 VOLTAGE Register
        43. 9.6.2.43 CHANNEL 3 VOLTAGE Register
        44. 9.6.2.44 CHANNEL 4 VOLTAGE Register
        45. 9.6.2.45 2x FOLDBACK SELECTION Register
        46.       93
        47. 9.6.2.46 FIRMWARE REVISION Register
        48. 9.6.2.47 I2C WATCHDOG Register
        49. 9.6.2.48 DEVICE ID Register
        50. 9.6.2.49 CHANNEL 1 DETECT RESISTANCE Register
        51. 9.6.2.50 CHANNEL 2 DETECT RESISTANCE Register
        52. 9.6.2.51 CHANNEL 3 DETECT RESISTANCE Register
        53. 9.6.2.52 CHANNEL 4 DETECT RESISTANCE Register
        54. 9.6.2.53 CHANNEL 1 DETECT CAPACITANCE Register
        55. 9.6.2.54 CHANNEL 2 DETECT CAPACITANCE Register
        56. 9.6.2.55 CHANNEL 3 DETECT CAPACITANCE Register
        57. 9.6.2.56 CHANNEL 4 DETECT CAPACITANCE Register
        58. 9.6.2.57 CHANNEL 1 ASSIGNED CLASS Register
        59. 9.6.2.58 CHANNEL 2 ASSIGNED CLASS Register
        60. 9.6.2.59 CHANNEL 3 ASSIGNED CLASS Register
        61. 9.6.2.60 CHANNEL 4 ASSIGNED CLASS Register
        62. 9.6.2.61 AUTO CLASS CONTROL Register
        63. 9.6.2.62 CHANNEL 1 AUTO CLASS POWER Register
        64. 9.6.2.63 CHANNEL 2 AUTO CLASS POWER Register
        65. 9.6.2.64 CHANNEL 3 AUTO CLASS POWER Register
        66. 9.6.2.65 CHANNEL 4 AUTO CLASS POWER Register
        67. 9.6.2.66 ALTERNATIVE FOLDBACK Register
        68. 9.6.2.67 SRAM CONTROL Register
          1. 9.6.2.67.1 SRAM START ADDRESS (LSB) Register
          2. 9.6.2.67.2 SRAM START ADDRESS (MSB) Register
          3. 9.6.2.67.3 118
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Autonomous Operation
      2. 10.1.2 Introduction to PoE
        1. 10.1.2.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Connections on Unused Channels
        2. 10.2.2.2 Power Pin Bypass Capacitors
        3. 10.2.2.3 Per Port Components
        4. 10.2.2.4 System Level Components (not Shown in the Schematic Diagrams)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 VDD
    2. 11.2 VPWR
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Kelvin Current Sensing Resistors
      2.      138
    2. 12.2 Layout Example
      1. 12.2.1 Component Placement and Routing Guidelines
        1. 12.2.1.1 Power Pin Bypass Capacitors
        2. 12.2.1.2 Per-Port Components
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

Conditions are –40 < T < 125 °C unless otherwise noted.VVDD = 3.3 V,VVPWR = 54 V, VDGND = VAGND,DGND, KSENSA, KSENSB, KSENSC and KSENSD connected to AGND, and all outputs are unloaded, 2xFBn =0.  Positive currents are into pins. RS = 0.200 Ω, to KSENSA (SEN1 orSEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to KSENSD (SEN7 or SEN8). Typical values are at 25 °C. All voltages are with respect to AGND unless otherwise noted. Operating registers loaded with default values unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT SUPPLY VPWR
IVPWRVPWR Current consumptionVVPWR = 54 V1012.5mA
VUVLOPW_FVPWR UVLO falling thresholdCheck internal oscillator stops operating14.517.5V
VUVLOPW_RVPWR UVLO rising threshold15.518.5V
VPUV_FVPWR Undervoltage falling thresholdVPUV threshold2526.528V
INPUT SUPPLY VDD
IVDDVDD Current consumption612mA
VUVDD_FVDD UVLO falling thresholdFor channel deassertion2.12.252.4V
VUVDD_RVDD UVLO rising threshold2.452.62.75V
VUVDD_HYSHysteresis VDD UVLO0.35V
VUVW_FVDD UVLO warning thresholdVDD falling2.62.83V
A/D CONVERTERS
TCONV_IConversion timeAll ranges, each channel0.640.80.96ms
TCONV_VConversiontimeAll ranges, each channel0.821.031.2ms
TINT_CURIntegration time, CurrentEach channel, channel ON current82102122ms
TINT_DETIntegration time, Detection13.116.620ms
TINT_channelVIntegration time, Channel Voltagechannel powered3.254.124.9ms
TINT_inVIntegration time, Input Voltage3.254.124.9ms
Input voltage conversion scale factor and accuracyVVPWR = 57 V151751556515955Counts
55.575758.43V
VVPWR = 44 V117131201512316Counts
42.894445.10V
Powered Channel voltage conversion scale factor and accuracyVVPWR - VDRAINn = 57 V151751556515955Counts
55.575758.43V
VVPWR - VDRAINn = 44 V117131201512316Counts
42.894445.10V
δV/VChannelVoltage reading accuracy–2.52.5%
Powered Channel current conversion scale factor and accuracyChannel current = 770 mA843186048776Counts
754.5770785.4mA
Channel Current = 100 mA108411181152Counts
97100103mA
δI/IChannelCurrent reading accuracyChannel Current = 100 mA–33%
Channel Current = 770 mA–22
δR/RChannelResistance reading accuracy15 kΩ ≤ RChannel ≤ 33 kΩ, CChannel ≤ 0.25 µF–77%
IbiasSense Pin bias currentChannel ON or during class–2.50µA
GATE 1-8
VGOHGate drive voltageVGATEn , IGATE = –1 µA1012.5V
IGO-Gate sinking current with Power-on Reset, OSS detected or channel turnoff commandVGATEn = 5 V60100190mA
IGO short-Gate sinking current with channel short-circuitVGATEn = 5 V,
VSENn  ≥ Vshort (or Vshort2X if 2X mode)
60100190mA
IGO+Gate sourcing currentVGATEn = 0 V, default selection395063µA
tD_off_OSSGate turnoff time from 1-bit OSS inputFrom OSS to VGATEn < 1 V,
VSENn = 0 V, MbitPrty = 0
15µs
tOSS_OFFGate turnoff time from 3-bit OSS inputFrom Start bit falling edge to VGATEn < 1 V,
VSENn = 0 V, MbitPrty = 1
72104µs
tP_off_CMDGate turnoff time from channel turnoff commandFrom Channel off command (POFFn = 1) to VGATEn < 1 V, VSENn = 0 V300µs
tP_off_RSTGate turnoff time with /RESETFrom /RESET low to VGATEn < 1 V, VSENn = 0 V15µs
DRAIN 1-8
VPGTPower-Good thresholdMeasured at VDRAINn12.133V
VSHTShorted FET thresholdMeasured at VDRAINn468V
RDRAINResistance from DRAINn to VPWRAny operating mode except during detection or while the Channel is ON, including in device RESET state80100190
AUTOCLASS
tClass_ACSStart of Autoclass DetectionMeasured from the start of Class90100ms
tAUTO_PSE1Start of Autoclass Power MeasurementMeasured from the end of Inrush1.41.6s
Measured from setting the MACx bit while channel is already powered10ms
tAUTODuration of Autoclass Power Measurement1.71.81.9s
tAUTO_windowAutoclass Power Measurement Sliding Window0.150.3s
PACAutoclass Channel Power conversion scale factor and accuracyVPWR = 52 V, VDRAINn = 0 V,
Channel current = 770 mA
768084Counts
VPWR = 50 V, VDRAINn = 0 V,
Channel current = 100 mA
91011
DETECTION
IDISCDetection currentFirst and 3rd detection points
VVPWR – VDRAINn = 0 V
145160190µA
2nd and 4th detection points VVPWR – VDRAINn = 0 V235270300
ΔIDISC2nd – 1st detection currentsVVPWR - VDRAINn = 0 V98110118µA
Vdet_openOpen circuit detection voltageMeasured as VVPWR – VDRAINn23.52629V
RREJ_LOWRejected resistance low range0.8615
RREJ_HIRejected resistance high range33100
RACCEPTAccepted resistance range192526.5
RSHORTShorted Channel threshold360Ω
ROPENOpen Channel Threshold400
tDETDetection DurationTime to complete a detection275350425ms
tDET_BOFFDetect backoff pause between discovery attemptsVVPWR – VDRAINn > 2.5 V300400500ms
VVPWR – VDRAINn < 2.5 V20100ms
tDET_DLYDetection delayFrom command or PD attachment to Channel detection complete590ms
Capacitance MeasurementCport = 10uF8.51011.5uF
CLASSIFICATION
VCLASSClassification VoltageVVPWR – VDRAINn, VSENn ≥ 0 mV
Ichannel ≥ 180 µA
15.518.520.5V
ICLASS_LimClassification Current LimitVVPWR – VDRAINn = 0 V657590mA
ICLASS_THClassification Threshold CurrentClass 0-158mA
Class 1-21316mA
Class 2-32125mA
Class 3-43135mA
Class 4-Class overcurrent4551mA
tLCEClassification Duration (1st Finger)From detection complete95105ms
tCLE2/3Classification Duration (2nd & 3th Finger)From Mark complete6.512ms
MARK
VMARKMark Voltage4 mA ≥ IChannel ≥ 180 µA
VVPWR – VDRAINn
710V
IMARK_LimMark Sinking Current LimitVVPWR – VDRAINn = 0 V607590mA
tMEMark Duration612ms
DC DISCONNECT
VIMINDC disconnect threshold0.81.31.8mV
tMPDOPD Maintain Power signature dropout time limitTMPDO = 00320400ms
TMPDO = 0175100ms
TMPDO = 10150200ms
TMPDO = 11600800ms
tMPSPD Maintain Power Signature time for validity2.53ms
PORT POWER POLICING
δPCUT/PCUTPCUT tolerance< 15 W0612%
δPCUT/PCUTPCUT tolerance≥ 15 W048%
tOVLDPCUT time limitTOVLD = 005070ms
TOVLD = 012535
TOVLD = 10100140
TOVLD = 11200280
PORT CURRENT INRUSH
VInrushIInrush limit, ALTIRNn = 0VVPWR – VDRAINn = 1 V193041mV
VVPWR – VDRAINn = 10 V193041
VVPWR – VDRAINn = 15 V334455
VVPWR – VDRAINn = 30 V8090
VVPWR – VDRAINn = 55 V8090
IInrush limit, ALTIRNn = 1VVPWR – VDRAINn = 1 V193041
VVPWR – VDRAINn = 10 V364758
VVPWR – VDRAINn = 15 V536475
VVPWR – VDRAINn = 30 V8090
VVPWR – VDRAINn = 55 V8090
tSTARTMaximum current limit duration in start-upTSTART = 005070ms
TSTART = 012535
TSTART = 10100140
PORT CURRENT FOLDBACK
VLIMILIM 1X limit, 2xFB = 0 and ALTFBn = 0VDRAINn = 1 V8090mV
VDRAINn = 15 V8090
VDRAINn = 30 V515865
VDRAINn = 50 V233037
ILIM 1X limit, 2xFB = 0 and ALTFBn = 1VDRAINn = 1 V8090
VDRAINn = 25 V8090
VDRAINn = 40 V455157
VDRAINn = 50 V233037
VLIM2XILIM 2X limit, 2xFB = 1 and ALTFBn = 0VDRAINn = 1 V245250262mV
VDRAINn = 10 V164180196
VDRAINn = 30 V515864
VDRAINn = 50 V233037
ILIM 2X limit, 2xFB = 1 and ALTFBn = 1VDRAINn = 1 V245250262
VDRAINn = 20 V139147155
VDRAINn = 40 V455157
VDRAINn = 50 V233037
tLIMILIM time limit2xFBn = 0556065ms
2xFBn = 1TLIM = 00556065
TLIM = 01151617
TLIM = 10101112
TLIM = 1166.57
SHORT CIRCUIT DETECTION
VshortISHORT threshold in 1X mode and during inrush205245mV
Vshort2XISHORT threshold in 2X mode280320
tD_off_SENGate turnoff time from SENn input2xFBn = 0, VDRAINn = 1 V
From VSENn pulsed to 0.425 V.
0.9µs
2xFBn = 1, VDRAINn = 1 V
From VSENn pulsed to 0.62 V.
0.9
CURRENT FAULT RECOVERY (BACKOFF) TIMING
tedError delay timing. Delay before next attempt to power a channel following power removal due to error conditionPCUT , ILIM or IInrush fault semiauto mode0.811.2s
δIfaultDuty cycle of Ichannel with current fault5.56.7%
THERMAL SHUTDOWN
Shutdown temperatureTemperature rising135146°C
Hysteresis7°C
DIGITAL I/O (SCL, SDAI, A1-A4, /RESET, OSS unless otherwise stated)
VIHDigital input High2.1V
VILDigital input Low0.9V
VIT_HYSInput voltage hysteresis0.17V
VOLDigital output LowSDAO at 9mA0.4V
Digital output Low/INT at 3mA0.4V
RpullupPullup resistor to VDD/RESET, A1-A4, TEST0305080
RpulldownPulldown resistor to DGNDOSS, TEST1, TEST2305080
tFLT_INTFault to /INT assertionTime to internally register an Interrupt fault, from Channel turn off50500µs
TRESETmin/RESET input minimum pulse width5µs
Tbit_OSS3-bit OSS bit periodMbitPrty = 1242526µs
tOSS_IDLIdle time between consecutive shutdown code transmission in 3-bit modeMbitPrty = 14850µs
tr_OSSInput rise time of OSS in 3-bit mode0.8 V → 2.3 V, MbitPrty = 11300ns
tf_OSSInput fall time of OSS in 3-bit mode2.3 V → 0.8 V, MbitPrty = 11300ns
I2C TIMING REQUIREMENTS
tPORDevice power-on reset delay20ms
fSCLSCL clock frequency10400kHz
tLOWLOW period of the clock0.5µs
tHIGHHIGH period of the clock0.26µs
tfoSDAO output fall timeSDAO, 2.3 V → 0.8 V, Cb = 10 pF, 10 kΩ pull-up to 3.3 V1050ns
SDAO, 2.3 V → 0.8 V, Cb = 400 pF, 1.3 kΩ pull-up to 3.3 V1050ns
CI2CSCL capacitance10pF
CI2C_SDASDAI, SDAO capacitance6pF
tSU,DATWData setup tme (Write operation)50ns
tHD,DATWData hold time (Write operation)0ns
tHD,DATRData hold time (Read operation)150400ns
tfSDAInput fall times of SDAI2.3 V → 0.8 V20120ns
trSDAInput rise times of SDAI0.8 V → 2.3 V20120ns
trInput rise time of SCL0.8 V → 2.3 V20120ns
tfInput fall time of SCL2.3 V → 0.8 V20120ns
tBUFBus free time between a STOP and START condition0.5µs
tHD,STAHold time After (Repeated) START condition0.26µs
tSU,STARepeated START condition setup time0.26µs
tSU,STOSTOP condition setup time0.26µs
tDGSuppressed spike pulse width, SDAI and SCL50ns
tWDT_I2CI2C Watchdog trip delay1.12.23.3sec