SBVS251A January   2015  – February 2024 TPS3702

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input (SENSE)
      2. 6.3.2 Outputs (UV, OV)
      3. 6.3.3 User-Configurable Accuracy Band (SET)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation (VDD > UVLO)
      2. 6.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
      3. 6.4.3 Power-On Reset (VDD < V(POR))
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Window Voltage Detector Considerations
      2. 7.1.2 Input and Output Configurations
      3. 7.1.3 Immunity to SENSE Pin Voltage Transients
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Evaluation Module
      2. 10.1.2 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.1 Input (SENSE)

The TPS3702 combines two comparators with a precision reference voltage and a trimmed resistor divider. Only a single external input is monitored by the two comparators because the resistor divider is internal to the device. This configuration optimizes device accuracy because all resistor tolerances are accounted for in the accuracy and performance specifications. Both comparators also include built-in hysteresis that provides some noise immunity and maintains stable operation.

The SENSE input can vary from ground to 6.5V (7.0V, absolute maximum), regardless of the device supply voltage used. Although not required in most cases, for noisy applications good analog design practice is to place a 1nF to 10nF bypass capacitor at the SENSE input to reduce sensitivity to transient voltages on the monitored signal.

For the undervoltage detector, the undervoltage output is driven to logic low when the SENSE voltage drops below the undervoltage falling threshold, VIT–(UV). When the voltage exceeds the undervoltage rising threshold, VIT+(UV) (which is VIT-(UV) + VHYS), the undervoltage output goes to a high-impedance state; see Figure 5-1.

For the overvoltage detector, the overvoltage output is driven to logic low when the voltage at SENSE exceeds the overvoltage rising threshold, VIT+(OV). When the voltage drops below the overvoltage falling threshold, VIT–(OV) (which is VIT+(OV) – VHYS), the overvoltage output goes to a high-impedance state; see Figure 5-1. Together, these two comparators form a window voltage detector function as described in the Section 7.1.1 section. Also see the Section 10.1.2 section.