SBVS085J January   2007  – June 2017

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Immunity to SENSE Pin Voltage Transients
      2. 8.3.2 SENSE Input
      3. 8.3.3 Manual Reset (MR) Input
      4. 8.3.4 Selecting the Reset Delay Time
    4. 8.4 Device Functional Modes
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description

Overview

The TPS3808Gxx-Q1 devices are low-current supervisory circuits used to monitor system voltages ranging from
0.4 V to 5 V. The devices assert an active low, open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin is asserted to a logic low. The RESET output remains low for the user-adjustable delay time after the SENSE voltage and MR return above their thresholds. The devices are also designed to be immune to short negative transients on the SENSE pin. The reset delay time can be configured by using the CT pin. The delay can be configured to 20 ms by leaving the CT pin floating, it can be configured to 300 ms by connecting the CT pin to VDD using a resistor, or can be configured from 1.25 ms to 10 s by connecting the CT pin to an external capacitor.

Functional Block Diagrams

TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1 TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1 fbd_adj_bvs085.gif
Figure 6. Adjustable-Voltage Version
TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1 TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1 fbd_bvs085.gif Figure 7. Fixed-Voltage Version

Feature Description

Immunity to SENSE Pin Voltage Transients

The TPS3808Gxx-Q1 is relatively immune to short negative transients on the SENSE pin. Sensitivity to transients is dependent on threshold overdrive, as shown in the Maximum Transient Duration at Sense vs Sense Threshold Overdrive Voltage graph (Figure 9). This graph shows the duration that the transient is below VIT compared to the magnitude of the voltage drop below VIT, or overdrive voltage. The overdrive voltage is expressed as a percentage of the VIT threshold value. Any combination of transient duration and overdrive voltage that lies above the curve results in RESET being asserted low. Any transient that lies below the curve is ignored by the device.

TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1 TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1 Overdrive_Voltage_sbvs085.gif Figure 8. Threshold Overdrive Voltage
TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1 TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1 vo_shto_bvs050.gif
Figure 9. Maximum Transient Duration at Sense vs Sense Threshold Overdrive Voltage

SENSE Input

The SENSE input provides a terminal at which any system voltage can be monitored. If the voltage on this pin drops below VIT, RESET is asserted low. The comparator has a built-in hysteresis to ensure smooth RESET assertions and deassertions. It is good analog design practice to put a 1-nF to 10-nF bypass capacitor on the SENSE input to reduce sensitivity to transients and layout parasitics.

The TPS3808G01-Q1 can be used to monitor any voltage rail down to 0.405 V using the circuit shown in Figure 10.

TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1 TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1 tc5_tps3808_bvs085.gif Figure 10. Using the TPS3808G01-Q1 to Monitor a User-Defined Threshold Voltage

Manual Reset (MR) Input

The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low (0.3 VDD) on MR causes RESET to assert low. After MR returns to a logic high and SENSE is above its reset threshold, RESET is deasserted high after the user-defined reset delay expires. MR is internally tied to VDD using a 90-kΩ resistor, so this pin can be left unconnected if MR is not used.

See Figure 11 for how MR can be used to monitor multiple system voltages. If the logic signal driving MR does not go fully to VDD, there will be some additional current draw into VDD as a result of the internal pullup resistor on MR. To minimize current draw, a logic-level FET can be used as shown in Figure 12.

TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1 TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1 tc2_tps3808_bvs085.gif Figure 11. Using MR to Monitor Multiple System Voltages
TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1 TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1 tc3_tps3808_bvs085.gif Figure 12. Using an External MOSFET to Minimize IDD When MR Signal Does Not Go to VDD

Selecting the Reset Delay Time

The TPS3808Gxx-Q1 device has three options for setting the RESET delay time as shown in Figure 13. Figure 13 (a) shows the configuration for a fixed 300-ms typical delay time by tying CT to VDD; a resistor from 40 kΩ to 200 kΩ must be used. Supply current is not affected by the choice of resistor. Figure 13 (b) shows a fixed 20-ms delay time by leaving the CT pin open. Figure 13 (c) shows a ground referenced capacitor connected to CT for a user-defined program time from 1.25 ms to 10 s.

TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1 TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1 tc4_tps3808_bvs085.gif Figure 13. Configuration Used to Set the RESET Delay Time

The capacitor CT should be ≥100 pF nominal value for the TPS3808Gxx-Q1 to recognize the capacitor is present. Use Equation 1 to calculate the capacitor value for a given delay time.

Equation 1. TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1 TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1 q_ct_bvs085.gif

The reset delay time is determined by the time it takes an on-chip precision 220-nA current source to charge the external capacitor to 1.23 V. When RESET asserts low, the capacitor is discharged. When the RESET conditions are cleared, the internal current source is enabled and begins to charge the external capacitor. When the voltage on this capacitor reaches 1.23 V, RESET deasserts. A low-leakage type capacitor such as a ceramic should be used and that stray capacitance around this pin may cause errors in the reset delay time.

Device Functional Modes

Whenever MR pin is set to a logic high and the SENSE input pin is higher than VIT, the open-drain RESET signal is deasserted high. If MR pin is set to a logic low or the SENSE input pin falls lower than VIT, then RESET is asserted low. Table 1 is a truth table that describes these operating modes.

Table 1. Truth Table

MR SENSE > VIT RESET
L 0 L
L 1 L
H 0 L
H 1 H