SBVS286A March   2017  – September 2021 TPS3851-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 RESET
      2. 7.3.2 Manual Reset MR
      3. 7.3.3 UV Fault Detection
      4. 7.3.4 Watchdog Mode
        1. 7.3.4.1 CWD
        2. 7.3.4.2 Watchdog Input WDI
        3. 7.3.4.3 Watchdog Output WDO
        4. 7.3.4.4 SET1
    4. 7.4 Device Functional Modes
      1. 7.4.1 VDD is Below VPOR ( VDD < VPOR)
      2. 7.4.2 Above Power-On-Reset, But Less Than VDD(min) (VPOR ≤ VDD < VDD(min))
      3. 7.4.3 Normal Operation (VDD ≥ VDD(min))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 CWD Functionality
        1. 8.1.1.1 Factory-Programmed Timing Options
        2. 8.1.1.2 Adjustable Capacitor Timing
      2. 8.1.2 Overdrive Voltage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Monitoring the 1.8-V Rail
        2. 8.2.2.2 Calculating the RESET and WDO Pullup Resistor
        3. 8.2.2.3 Setting the Watchdog
        4. 8.2.2.4 Watchdog Disabled During Initialization Period
      3. 8.2.3 Glitch Immunity
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.4 Watchdog Disabled During Initialization Period

The watchdog is often needed to be disabled during startup to allow for an initialization period. When the initialization period is over, the watchdog timer is turned back on to allow the microcontroller to be monitored by the TPS3851-Q1. To achieve this setup, SET1 must start at GND. In this design, SET1 is controlled by a TPS3890-Q1 supervisor. In this application, the TPS3890-Q1 was chosen to monitor VDD as well, which means that the RESET on the TPS3890-Q1 stays low until VDD rises above VITN. When VDD comes up, the delay time can be adjusted through the CT capacitor on the TPS3890-Q1. With this approach, the RESET delay can be adjusted from a minimum of 25 μs to a maximum of 30 seconds. For this design, a typical delay of 5 seconds is needed before the watchdog timer is enabled. The CT capacitor calculation (see the TPS3890-Q1 data sheet) yields an ideal capacitance of 4.67 μF, giving a closest standard ceramic capacitor value of 4.7 μF. When connecting a 4.7-μF capacitor from CT to GND, the typical delay time is 5 seconds. Figure 8-5 shows that when the watchdog is disabled, the WDO output remains high. However when SET1 goes high and there is no WDI signal, WDO begins to assert. See the TPS3890-Q1 data sheet for detailed information on the TPS3890-Q1.