SNVSCC2E November   2022  – May 2024 TPS389C03-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I2C
      2. 7.3.2  Maskable Interrupt (AMSK)
      3. 7.3.3  VDD
      4. 7.3.4  MON
      5. 7.3.5  NRST
      6. 7.3.6  NIRQ
      7. 7.3.7  ADC
      8. 7.3.8  Packet Error Checking (PEC)
      9. 7.3.9  Q&A Watchdog
        1. 7.3.9.1 Question and Token Generation
        2. 7.3.9.2 Q&A Watchdog Open and Close Window Delay
        3. 7.3.9.3 Q&A Watchdog Status Register
        4. 7.3.9.4 Q&A Watchdog Timing
        5. 7.3.9.5 Q&A Watchdog State Machine and Test Program
      10. 7.3.10 Error Signal Monitoring (ESM)
        1. 7.3.10.1 ESM Timing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS389C03-Q1 Power ON
  9. 8 Register Maps
    1. 8.1 Registers Overview
      1. 8.1.1 BANK0 Registers
      2. 8.1.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Guidelines
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Documentation Support
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Device Functional Modes

The TPS389C03-Q1 has three key functional modes that the device may enter over the course of operation. When no power is applied to the device, it will be in the OFF state where the monitoring channels and the watchdog will be inactive. Once VDD is greater than UVLO, the device will enter the ACTIVE state after the BIST and OTP loading have finished. During the ACTIVE state, the device will be capable of full monitoring and the watchdog will be active. If a BIST failure, double-error detect (DED) during the OTP loading, thermal shutdown, or an address pin fault occurs, the device will enter the FAILSAFE mode. Once in FAILSAFE, NRST and NIRQ are asserted low. To leave the FAILSAFE state, power to the TPS389C03-Q1 must be cycled. Reading register 0x30 in BANK0 provides information on the state of the device. See Section 8.1.1.10 for details. The state diagram drawn in Figure 7-30 follows the progression through each state.

TPS389C03-Q1 TPS389C03-Q1 State DiagramFigure 7-30 TPS389C03-Q1 State Diagram