10.1 Layout Guidelines

Grounding and PCB Circuit Layout Considerations

1. Connect the drains of TOP_SW1 and TOP_SW2 together with the +ve terminal of the input capacitor C_OUT1. The trace length between these terminals should be short.
2. The Kelvin-current sensing for the shunt resistor should have traces with minimum spacing, routed in parallel with each other. Place any filtering capacitors for noise near the IC pins.
3. Connect the resistor divider for sensing output voltage between the +ve terminal of its respective output capacitor C_Buck1 or C_Buck2 or C_Buck3 and the IC signal ground. Do not route these components or their traces near any switching nodes or high-current traces.

Other Considerations

1. Separate the IC signal ground and power ground terminals (GND and PGNDx) pins. Use a star-ground configuration if connecting to a non-ground plane system. Use tie-ins for the EXTSUP capacitor, compensation network ground, and voltage-sense feedback ground networks to this star ground.
2. Connect a compensation network between the compensation pins and IC signal ground. Connect the oscillator resistor (frequency setting) between the RT pin and IC signal ground. Do not locate these sensitive circuits near the dV/dt nodes; these include the gate drive outputs, phase pins, and boost circuits (bootstrap).
3. Reduce the surface area of the high-current-carrying loops to a minimum by ensuring optimal component placement. Locate the bypass capacitors as close as possible to their respective power and ground pins.

10.2 Layout Example

10.3 Power Dissipation

The power dissipation depends on the MOSFET drive current and input voltage. The drive current is proportional to the total gate charge of the external MOSFET.

10.3.2 Power Dissipation of Buck Converter Buck3 (V_OUT3)

10.3.2.1 High-Side Switch

The power dissipation losses are applicable for positive output currents:

Equation 47. P_HS-CON = I_OUTr² × r_DS(on) × (V_OUT / V_IN) (Conduction losses)

Equation 48. P_{HS_SW} = ½ × V_SUP × I_OUT × (t_r + t_f) × f_SW (Switching losses)

P_{HS_Gate} = 1 nC × f_sw (Gate drive losses, valid at V_REG = 5.8 V, V_SUP = 4 V)

Equation 49. P_{HS_Total} = P_HS-CON + P_{H_SW} + P_{HS_Gate}

10.3.2.2 Low-Side Switch

The power dissipation losses are applicable for positive output currents.

Equation 50. P_LS-CON = I_OUTr² × r_DS(on) × ( 1 – V_OUT / V_IN) (Conduction losses)

Equation 51. P_{LS_SW} = ½ × V_SUP × I_OUT × (t_r + t_f) × f_SW (Switching losses)

Equation 52. P_{LS_Gate} = 1 nC × f_sw (Gate drive losses, valid at V_VREG = 5.8 V, V_SUP = 4 V)

Equation 53. P_{LS_DIODE} = 2 × V_f × I_OUT × f_sw × t_dead (Low-side body diode losses during dead time)

Equation 54. P_{LS_Total} = P_LS-CON + P_{L_SW} + P_{LS_Gate} + P_{LS_DIODE}

10.3.2.3 Linear Regulator (LREG1)

Equation 55. P_LREG1 = (V_VLR1 – V_LREG1) × I_OUT

where

• V_OUT = Output voltage, V_IN = Input voltage
• I_OUT = Output current, f_SW = Switching frequency
• t_r = Rise time of switching node PH3
• t_f = Fall time of switching node PH3
• V_REG = FET gate drive voltage
• Vf_diode = Low-side FET diode drop (conduction during dead time)

10.3.2.4 IC Power Consumption

Equation 56. P_IC = Iq × V_IN (Watts)

Equation 57. P_Total = P_{Buck1 and Buck2} + P_{HS_Total} + P_{LS_Total} + P_LREG1+ P_IC (Watts)

Table 2. Summary of Equations for Component Selection⁽¹⁾⁽²⁾

PARAMETER OR COMPONENT	Buck1 AND Buck2	Buck3	COMMENTS
Duty cycle D			Buck3 is powered from Buck1 or Buck2.
Current-limit sense resistor RS		Not Applicable	Choose a current limit of 25% more than maximum load.
Inductor selection L			Choose RS based on the current limit set for the application.
Inductor ripple current			Typically the ± inductor ripple current is 25% of maximum load current.
Output capacitor COUT			Also consider that the ESR of the output capacitor influences the output-voltage ripple due to load steps.
Input capacitor CIN			Base the input-capacitor value on the input-voltage ripple desired.
Soft-start CSS			Choose the soft-start time required, ∆t, and then calculate CSS.
Bootstrap capacitor CBoot			Choose based on the desired amount of ripple based on FET gate charge and operating VIN.
Compensation resistor for GBW			To determine resistor R3, assume GBW ≈ fsw / 5 to fsw / 20.
Compensation capacitor for zero			C1 can be also increased 2× for faster small-signal settling at the expense of large step response (slew rate on COMPx).
Compensation capacitor for second pole			The value of C2 is also critical for buffering the noise on the COMPx pin, and so the value of capacitance is a trade-off between noise immunity and phase margin.
Pole at low frequency with high dc gain			ROUT_OTA = 1 MΩ minimum
Zero at control-loop pole related to output filter LC			Place zero at 0.05 to 0.1 × GBW (see comment on C1 above).
Second pole for type 2a			Place the second pole at or below half of the switching frequency ƒsw, observing distance to GBW.

(1) K_CFB = 0.125 / R_SENSE

(2) ß = V_REF / V_OUT

Figure 24. Power Dissipation Derating Profile Based on High-K JEDEC PCB

10.4 Thermal Considerations

The TPS43340-Q1 is protected from overtemperature using an internal thermal shutdown circuit. If the die temperature exceeds the thermal shutdown threshold (for example, due to fault conditions such as a short circuit at the gate drivers or VREG), the device turns off, and restarts when the temperature has fallen by the hysteresis.

The synchronous buck converter Buck3 with the integrated FETs does not support LPM. Turning on Buck3 forces the system to operate in normal mode, and the quiescent current consumption increases.

Monitoring of the threshold for the charge pump of the low quiescent linear regulator LREG1 to be turned on occurs at the VIN pin. If using LREG1 as post regulator with an input voltage V_LR1 of less than 7.5 V, the charge pump still stays off if operating within the required conditions for V_IN and the load current. The sampling interval for the foregoing voltage thresholds at the VIN pin is typically 60 µs.