Certain issues must be considered before designing a layout using the TPS51216-EP.

• VIN capacitors, VOUT capacitors, and MOSFETs are the power components and should be placed on one side of the PCB (solder side). Other small signal components should be placed on another side (component side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the small signal traces from noisy power lines.
• All sensitive analog traces and components such as VDDQSNS, VTTSNS, MODE, REFIN, VREF, and TRIP should be placed away from high-voltage switching nodes such as SW, DRVL, DRVH, or VBST to avoid coupling. Use internal layers as ground planes and shield feedback trace from power traces and components.
• The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to suppress generating switching noise.
  • The most important loop to minimize the area of is the path from the VIN capacitors through the high and low-side MOSFETs, and back to the capacitors through ground. Connect the negative node of the VIN capacitors and the source of the low-side MOSFET at ground as close as possible. (Refer to loop number 1 of Figure 11-1)
  • The second important loop is the path from the low-side MOSFET through inductor and VOUT capacitors, and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFET and negative node of VOUT capacitors at ground as close as possible. (Refer to loop number 2 of Figure 11-1)
  • The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side MOSFET, high current flows from V5IN capacitor through gate driver and the low-side MOSFET, and back to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current flows from gate of the low-side MOSFET through the gate driver and PGND, and back to source of the low-side MOSFET through ground. Connect negative node of V5IN capacitor, source of the low-side MOSFET and PGND at ground as close as possible. (Refer to loop number 3 of Figure 11-1)
• Because the TPS51216-EP controls output voltage referring to voltage across VOUT capacitor, VDDQSNS should be connected to the positive node of VOUT capacitor. In a same manner GND should be connected to the negative node of VOUT capacitor.
• Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling to a high-voltage switching node.
• Connect the frequency and mode setting resistor from MODE pin to ground, and make the connections as close as possible to the device. The trace from the MODE pin to the resistor and from the resistor to ground should avoid coupling to a high-voltage switching node
• Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and vias of at least 0.5 mm (20 mils) diameter along this trace.
• The PCB trace defined as SW node, which connects to the source of the switching MOSFET, the drain of the rectifying MOSFET and the high-voltage side of the inductor, should be as short and wide as possible.
• VLDOIN should be connected to VDDQ output with short and wide traces. An input bypass capacitor should be placed as close as possible to the pin with short and wide　connections.
• The output capacitor for VTT should be placed close to the pin with a short and wide connection in order to　avoid additional ESR and/or ESL of the trace.
• VTTSNS should be connected to the positive node of the VTT output capacitors as a separate trace from the high-current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to　sense the voltage at the point of the load, it is recommended to attach the output capacitors at that point. Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and the output capacitors.
• Consider adding a low pass filter (LPF) at VTTSNS in case the ESR of the VTT output capacitors is larger than 2 mΩ.
• VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference voltage of VTTREF. Avoid any noise generative lines.
• The negative node of the VTT output capacitors and the VTTREF capacitor should be tied together by avoiding　common impedance to high-current path of the VTT source/sink current.
• GND pin node represents the reference potential for VTTREF and VTT outputs. Connect GND　to negative nodes of VTT capacitors, VTTREF capacitor and VDDQ capacitors with care to avoid additional ESR and/or ESL. GND and PGND should be connected together at a single point.
• In order to effectively remove heat from the package, prepare the thermal land and solder to the package thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading. Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal/solder-side ground planes should be used to help dissipation.