SLVSAE4A July   2010  – August 2014 TPS53128

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 16
      2. 7.2.2 17
    3. 7.3 Feature Description
      1. 7.3.1  PWM Operation
      2. 7.3.2  Light-Load Condition
      3. 7.3.3  Drivers
      4. 7.3.4  PWM Frequency And Adaptive On-Time Control
      5. 7.3.5  5-Volt Regulator
      6. 7.3.6  Soft Start
      7. 7.3.7  Pre-Bias Support
      8. 7.3.8  Output Discharge Control
      9. 7.3.9  Over Current Limit
      10. 7.3.10 Over/Under Voltage Protection
      11. 7.3.11 UVLO Protection
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

TPS53128 qfn_po_lvs947.gif
TPS53128 tssop_po_lvs947.gif

Table 2. Pin Functions

PIN I/O DESCRIPTION
NAME RGE PW
VBST1, VBST2 23, 8 2, 11 I Supply input for high-side NFET driver. Bypass to SWx with a high-quality 0.1-μF ceramic capacitor. An external schottky diode can be added from VREG5 if forward drop is critical to drive the high-side FET.
EN1, EN2 24, 7 3, 10 I Enable. Pull High to enable SMPS.
VO1, VO2 1, 6 4, 9 I Output voltage inputs for on-time adjustment and output discharge. Connect directly to the output voltage.
VFB1, VFB2 2, 5 5, 8 I D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
GND 3 6 I Signal ground pin. Connect to PGND1, PGND2 and system ground at a single point.
DRVH1, DRVH2 22, 9 1, 12 O High-side N-Channel MOSFET gate driver outputs. SWx referenced drivers switch between SWx (OFF) and VBSTx (ON).
SW1, SW2 21, 10 24, 13 I/O Switch node connections for both the high-side drivers and the over current comparators.
DRVL1, DRVL2 20, 11 23, 14 O Low-side N-Channel MOSFET gate driver outputs. PGND referenced drivers switch between PGNDx (OFF) and VREG5 (ON).
PGND1, PGND2 19, 12 22, 15 I/O Power ground connections for both the low-side drivers and the over current comparators. Connect PGND1, PGND2 and GND strongly together near the IC.
TRIP1, TRIP2 18, 13 21, 16 I Over current threshold programming pin. Connect to GND with a resistor to GND to set threshold for low-side RDS(ON) current limit.
VIN 17 20 I Supply Input for 5-V linear regulator. Bypass to GND with a minimum high-quality 0.1-μF ceramic capacitor.
V5FILT 15 18 I 5-V supply input for the entire control circuitry except the MOSFET drivers. Bypass to GND with a minimum high-quality 1.0-μF ceramic capacitor. V5FILT is connected to VREG5 via an internal 10-Ω resistor.
VREG5 16 19 O Output of 5-V linear regulator and supply for MOSFET drivers. Bypass to GND with a minimum high-quality 4.7-μF ceramic capacitor. VREG5 is connected to V5FILT via an internal 10-Ω resistor.
SS1, SS2 4,14 7, 17 O Soft-start programming pin. Connect capacitor from SSx pin to GND to program soft-start time.