SLVS875D January   2009  – September 2023 TPS54332

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics: Characterization Curves
    8. 6.8 Typical Characteristics: Supplemental Application Curves
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Voltage Reference (Vref)
      3. 7.3.3  Bootstrap Voltage (BOOT)
      4. 7.3.4  Enable and Adjustable Input Undervoltage Lockout (VIN UVLO)
      5. 7.3.5  Programmable Slow Start Using the SS Pin
      6. 7.3.6  Error Amplifier
      7. 7.3.7  Slope Compensation
      8. 7.3.8  Current Mode Compensation Design
      9. 7.3.9  Overcurrent Protection and Frequency Shift
      10. 7.3.10 Overvoltage Transient Protection
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN < 3.5 V
      2. 7.4.2 Operation With EN Control
      3. 7.4.3 Eco-mode
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Output Voltage Set Point
        4. 8.2.2.4  Input Capacitors
        5. 8.2.2.5  Output Filter Components
        6. 8.2.2.6  Inductor Selection
        7. 8.2.2.7  Capacitor Selection
        8. 8.2.2.8  Compensation Components
        9. 8.2.2.9  Bootstrap Capacitor
        10. 8.2.2.10 Catch Diode
        11. 8.2.2.11 Output Voltage Limitations
        12. 8.2.2.12 Power Dissipation Estimate
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Estimated Circuit Area
      4. 8.4.4 Electromagnetic Interference (EMI) Considerations
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Custom Design with WEBENCH® Tools
    2. 9.2 Support Resources
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Compensation Components

The external compensation used with the TPS54332 allows for a wide range of output filter configurations. A large range of capacitor values and types of dielectric are supported. The design example uses ceramic X5R dielectric output capacitors, but other types are supported.

TI recommends a type II compensation scheme for the TPS54332. The compensation components are chosen to set the desired closed-loop crossover frequency and phase margin for output filter components. The type II compensation has the following characteristics; a DC gain component, a low-frequency pole, and a mid-frequency zero or pole pair.

The DC gain is determined by Equation 16.

Equation 16. G D C = V G G M × V R E F V O

Where:

VGGM = 800
VREF = 0.8 V

The low-frequency pole is determined by Equation 17.

Equation 17. F P O = 1 2 × π × R O O × C Z

ROA = 8.696 MΩ.

The mid-frequency zero is determined by Equation 18.

Equation 18. F Z 1 = 1 2 × π × R Z × C Z

And, the mid-frequency pole is given by Equation 19.

Equation 19. F P 1 = 1 2 × π × R Z × C P

The first step is to choose the closed-loop crossover frequency. The closed-loop crossover frequency must be less than 1/8 of the minimum operating frequency, but for the TPS54332 TI recommends that the maximum closed-loop crossover frequency be not greater than 75 kHz. Next, the required gain and phase boost of the crossover network must be calculated. By definition, the gain of the compensation network must be the inverse of the gain of the modulator and output filter. For this design example, where the ESR zero is much higher than the closed-loop crossover frequency, the gain of the modulator and output filter can be approximated by Equation 20.

Equation 20. G a i n = - 20 × l o g 2 × π × R S E N S E × F C O × C O

Where:

RSENSE = 1 Ω / 12

FCO = Closed-loop crossover frequency

CO = Output capacitance

The phase loss is given by Equation 21.

Equation 21. P L = α × t a n 2 × π × F C O × R E S R × C O -   α × t a n 2 × π × F C O × R O × C O - 10 d B

Where:

RESR = Equivalent series resistance of the output capacitor

RO = VO/IO

The measured overall loop response for the circuit is given in Figure 8-9. Note that the actual closed-loop crossover frequency is higher than intended at about 25 kHz. This is primarily due to variation in the actual values of the output filter components and tolerance variation of the internal feed-forward gain circuitry. Overall the design has greater than 60 degrees of phase margin and is completely stable over all combinations of line and load variability.

Now that the phase loss is known the required amount of phase boost to meet the phase margin requirement can be determined. The required phase boost is given by Equation 22.

Equation 22. P B = P M - 90 d e g - P L

Where PM = the desired phase margin.

A zero, pole pair of the compensation network is placed symmetrically around the intended closed-loop frequency to provide maximum phase boost at the crossover point. The amount of separation can be determined by Equation 23 and the resultant zero and pole frequencies are given by Equation 24 and Equation 25.

Equation 23. k = t a n P B 2 + 45 d e g
Equation 24. F Z 1 = F C O k
Equation 25. F P 1 = F C O × k

The low-frequency pole is set so that the gain at the crossover frequency is equal to the inverse of the gain of the modulator and output filter. Due to the relationships established by the pole and zero relationships, the value of RZ can be derived directly by Equation 26.

Equation 26. R Z = 2 × π × F C O × V O × C O × R O A G M C O M P × V G G M × V R E F

Where:

VO = Output voltage

CO = Output capacitance

FCO = Desired crossover frequency

ROA = 8.696 MΩ

GMCOMP = 12 A/V

VGGM = 800

VREF = 0.8 V

With RZ known, CZ and CP can be calculated using Equation 27 and Equation 28.

Equation 27. C Z = 1 2 × π × F Z 1 × R Z
Equation 28. C P = 1 2 × π × F P 1 × R Z

For this design, the two 47-μF output capacitors are used. For ceramic capacitors, the actual output capacitance is less than the rated value when the capacitors have a DC bias voltage applied. This is the case in a DC/DC converter. The actual output capacitance can be as low as 54 μF. The combined ESR is approximately 0.001 Ω.

Using Equation 20 and Equation 21, the output stage gain and phase loss are equivalent as:

Gain = –6.94 dB

and

PL = –93.94 degrees

For 70 degrees of phase margin, Equation 22 requires 63.64 degrees of phase boost.

Equation 23, Equation 24, and Equation 25 are used to find the zero and pole frequencies of:

FZ1 = 11.57 kHz

And

FP1 = 216 kHz

RZ, CZ, and CP are calculated using Equation 26, Equation 27, and Equation 28.

Equation 29. RZ=2×π×50000×2.5×82×10-6×8.696×10612×800×0.8=72.92kΩ
Equation 30. C Z = 1 2 × π × 11570 × 75000 = 183 p F
Equation 31. C P = 1 2 × π × 216000 × 75000 = 9.8 p F

Using standard values for R3, C6, and C7 in the application schematic of Figure 8-1.

R3 = 75 kΩ

C6 = 180 pF

C7 = 10 pF