SLVSE78D March 2020 – July 2021 TPS548A29
PRODUCTION DATA
The TPS548A29 has an internal 4.5-V LDO featuring input from VIN and output to VCC. When the EN voltage rises above the enable threshold (typically 1.22 V), the internal LDO is enabled and starts regulating output voltage on the VCC pin. The VCC voltage provides the bias voltage for the internal analog circuitry and also provides the supply voltage for the gate drives.
The VCC pin needs to be bypassed with a 2.2-µF, at least 6.3-V rating ceramic capacitor. An external bias that is above the output voltage of the internal LDO can override the internal LDO. This enhances the efficiency of the converter because the VCC current now runs off this external bias instead of the internal linear regulator.
The VCC UVLO circuit monitors the VCC pin voltage and disables the whole converter when VCC falls below the VCC UVLO falling threshold. Maintaining a stable and clean VCC voltage is required for a smooth operation of the device.
The following are considerations when using an external bias on the VCC pin: