SLUSCE4A January   2017  – July 2017 TPS548B22

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 25-A FET
      2. 7.3.2 On-Resistance
      3. 7.3.3 Package Size, Efficiency and Thermal Performance
      4. 7.3.4 Soft-Start Operation
      5. 7.3.5 VDD Supply Undervoltage Lockout (UVLO) Protection
      6. 7.3.6 EN_UVLO Pin Functionality
      7. 7.3.7 Fault Protections
        1. 7.3.7.1 Current Limit (ILIM) Functionality
        2. 7.3.7.2 Overvoltage Protection (OVP) and Undervoltage Protection (UVP)
        3. 7.3.7.3 Out-of-Bounds Operation
        4. 7.3.7.4 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 DCAP3 Control Topology
      2. 7.4.2 DCAP Control Topology
    5. 7.5 Programming
      1. 7.5.1 Programmable Pin-Strap Settings
        1. 7.5.1.1 Frequency Selection (FSEL) Pin
        2. 7.5.1.2 VSEL Pin
        3. 7.5.1.3 DCAP3 Control and Mode Selection
        4. 7.5.1.4 Application Workaround to Support 4-ms and 8-ms SS Settings
      2. 7.5.2 Programmable Analog Configurations
        1. 7.5.2.1 RSP/RSN Remote Sensing Functionality
          1. 7.5.2.1.1 Output Differential Remote Sensing Amplifier
        2. 7.5.2.2 Power Good (PGOOD Pin) Functionality
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS548B22 1.5-V to 18-V Input, 1-V Output, 25-A Converter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Design Procedure
        1. 8.2.3.1  Switching Frequency Selection
        2. 8.2.3.2  Inductor Selection
        3. 8.2.3.3  Output Capacitor Selection
          1. 8.2.3.3.1 Minimum Output Capacitance to Ensure Stability
          2. 8.2.3.3.2 Response to a Load Transient
          3. 8.2.3.3.3 Output Voltage Ripple
        4. 8.2.3.4  Input Capacitor Selection
        5. 8.2.3.5  Bootstrap Capacitor Selection
        6. 8.2.3.6  BP Pin
        7. 8.2.3.7  R-C Snubber and VIN Pin High-Frequency Bypass
        8. 8.2.3.8  Optimize Reference Voltage (VSEL)
        9. 8.2.3.9  MODE Pin Selection
        10. 8.2.3.10 Overcurrent Limit Design.
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Mounting and Thermal Profile Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RVF|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RVF Package
40-Pin LQFN-CLIP With Thermal Pad
Top View
TPS548B22 pinout_slusce4.gif

Pin Functions

PIN I/O/P(1) DESCRIPTION
NO. NAME
1, 2, 3 NU O Not used pins.
4 EN_UVLO I Enable pin that can turn on the DC/DC switching converter. Use also to program the required PVIN UVLO when PVIN and VDD are connected together.
5 BOOT P Supply rail for high-side gate driver (boot terminal). Connect boot capacitor from this pin to SW node. Internally connected to BP via bootstrap PMOS switch.
6, 7, 26, 27 NC No connect.
8, 9, 10, 11, 12 SW I/O Output switching terminal of power converter. Connect the pins to the output inductor.
13, 14, 15, 16, 17, 18, 19, 20 PGND P Power ground of internal FETs.
21, 22, 23, 24, 25, PVIN P Power supply input for integrated power MOSFET pair.
28 VDD P Controller power supply input.
29 DRGND P Internal gate driver return.
30 AGND G Ground pin for internal analog circuits.
31 BP O LDO output
32 FSEL I Program switching frequency, internal ramp amplitude and SKIP or FCCM mode.
33 VSEL I Program the initial start-up and or reference voltage without feedback resistor dividers (from 0.6 V to 1.2 V in 50-mV increments).
34 MODE I Mode selection pin. Select the control mode (DCAP3 or DCAP), internal VREF operation, external REFIN and tracking operation and soft-start timing selection.
35 PGOOD O Open drain power-good status signal.
36 ILIM I/O Program overcurrent limit by connecting a resistor to ground.
37 RESV_TRK I Do not connect.
38 RSN I Inverting input of the differential remote sense amplifier.
39 RSP I Non-inverting input of the differential remote sense amplifier.
40 VOSNS I Output voltage monitor input pin.
(1) I = input, O = output, G = GND