SLIS132A October   2008  – March 2015 TPS55065-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Dissipation Ratings
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Switched-Mode Input/Output Terminals (L1, L2)
      2. 7.3.2  Supply Terminal (Vdriver)
      3. 7.3.3  Internal Supply Decoupling Terminal (Vlogic)
      4. 7.3.4  Input Voltage Monitoring Terminal (AIN)
      5. 7.3.5  Input Undervoltage Alarm Terminal (AOUT)
      6. 7.3.6  Reset Delay Timer Terminal (REST)
      7. 7.3.7  Reset Terminal (RESET)
      8. 7.3.8  Main Regulator Output Terminal (VOUT)
      9. 7.3.9  Low-Power-Mode Terminal (CLP)
      10. 7.3.10 Switch-Output Terminal (5Vg)
      11. 7.3.11 5Vg-Enable Terminal (5Vg_ENABLE)
      12. 7.3.12 Slew-Rate Control Terminals (SCR0, SCR1)
      13. 7.3.13 Modulator Frequency Setting (Terminal Rmod)
      14. 7.3.14 Ground Terminal (PGND)
      15. 7.3.15 Enable Terminal (ENABLE)
      16. 7.3.16 Bootstrap Terminals (CBOOT1 and CBOOT2)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clock Modulator
      2. 7.4.2 Buck/Boost Transitioning
      3. 7.4.3 Buck SMPS
      4. 7.4.4 Boost SMPS
      5. 7.4.5 Extension of the Input Voltage Range on V(driver)
      6. 7.4.6 Low-Power Mode
      7. 7.4.7 Temperature and Short-Circuit Protection
      8. 7.4.8 Switch Output Terminal (5Vg) Current Limitation
      9. 7.4.9 Soft Start
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Buck Mode
        2. 8.2.2.2 Boost Mode
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Inductor
      2. 10.1.2 Filter Capacitors
      3. 10.1.3 Traces and Ground Plane
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PWP HTSSOP Package
20 Pins
Top View
TPS55065-Q1 p0021-02.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
SCR1 1 I Programmable slew-rate control
Cboot2 2 I External bootstrap capacitor
Cboot1 3 I External bootstrap capacitor
Vdriver 4 I Input voltage source
L1 5 I Inductor input (an external Schottky diode(1) to GND must be connected to L1)
PGND 6 I Power ground
L2 7 I Inductor output
VOUT 8 O 5-V regulated output
5Vg 9 O Switched 5-V supply
AIN 10 I Programmable alarm setting
CLP 11 I/O Low-power operation mode (digital input)
RESET 12 O Reset function (open drain)
AOUT 13 O Alarm output (open drain)
REST 14 O Programmable reset timer delay
Rmod 15 I Main switching frequency modulation setting to minimize EMI
GND 16 I Ground
Vlogic 17 O Supply decoupling output (may be used as a 5-V supply for logic-level inputs)
ENABLE 18 I Switched-mode regulator enable/disable
5Vg_ENABLE 19 I Switched 5-V voltage regulator output enable/disable
SCR0 20 I Programmable slew-rate control
Exposed thermal pad — — Connect to GND or left floating.
(1) Maximum 0.4 V at 1 A at 125°C