SLVSBJ1B September   2012  – January 2017 TPS65051-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Operation
      2. 7.3.2  DCDC1 Converter
      3. 7.3.3  DCDC2 Converter
      4. 7.3.4  Dynamic Voltage Positioning
      5. 7.3.5  Soft Start
      6. 7.3.6  100% Duty-Cycle Low-Dropout Operation
      7. 7.3.7  Undervoltage Lockout
      8. 7.3.8  Mode Selection
      9. 7.3.9  Enable
      10. 7.3.10 RESET
      11. 7.3.11 Short-Circuit Protection
      12. 7.3.12 Thermal Shutdown
      13. 7.3.13 Low Dropout Voltage Regulators
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Save Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output-Voltage Setting
          1. 8.2.2.1.1 Converter 1 (DCDC1)
          2. 8.2.2.1.2 Converter 2 (DCDC2)
        2. 8.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 8.2.2.2.1 Inductor Selection
          2. 8.2.2.2.2 Output-Capacitor Selection
          3. 8.2.2.2.3 Input-Capacitor Selection
        3. 8.2.2.3 Low-Dropout Voltage Regulators (LDOs)
        4. 8.2.2.4 RESET
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resource
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The TPS65051-Q1 device has 2 DC-DC buck converters and 4 LDOs. Each DC-DC and LDO has enable pins, allowing external sequence control of the PMU rails. The device also has a RESET feature that is generated from a THRESHOLD comparator. This RESET signal can be used to reset or warn of power shutdown to the embedded mircocontroller or processor. The TPS65051-Q1 device makes power-system integration easy for a variety of embedded processors or FPGAs.

7.2 Functional Block Diagram

TPS65051-Q1 fbd51_SLVSBJ1.gif

7.3 Feature Description

7.3.1 Operation

The TPS65051-Q1 device has two synchronous step-down converters. The converters operate with 2.25-MHz (typical) fixed-frequency pulse-width modulation (PWM) at moderate to heavy load currents. At light load currents, the converters automatically enter power-save mode and operate with PFM (pulse-frequency modulation).

During PWM operation, the converters use a unique fast-response voltage-mode controller scheme with input voltage feed-forward to achieve good line and load regulation, allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch turns on, the inductor current ramps up until the current comparator trips, and the control logic turns off the switch. The current-limit comparator turns off the switch if the current exceeds the limit of the P-channel switch. After the adaptive dead time, which prevents shoot-through current, the N-channel MOSFET rectifier turns on, and the inductor current ramps down. The clock signal turning off the N-channel rectifier and turning on the on the P-channel switch initiates the next cycle.

The two DC-DC converters operate synchronized to each other, with converter 1 as the master. A 180° phase shift between converter 1 and converter 2 decreases the input rms current, allowing the use of smaller input capacitors.

7.3.2 DCDC1 Converter

An external resistor divider connected to FB_DCDC1 pin sets the converter 1 output voltage. See the Converter 1 (DCDC1) section for more details. The maximum output current is 1 A.

7.3.3 DCDC2 Converter

Connect the VDCDC2 pin directly to the DCDC2 converter output voltage. The DEFDCDC2 pin selects the DCDC2 converter output voltage. See the Converter 2 (DCDC2) section for more details. The maximum output current is 600 mA.

An external resistor divider sets the output voltage. Connect the DEFDCDC2 pin to the external resistor divider.

7.3.4 Dynamic Voltage Positioning

This feature reduces the voltage under- and overshoots at load steps from light to heavy load and vice versa. It is activated In the power-save mode of operation, running the converter in PFM mode activates dynamic voltage positioning. Dynamic voltage positioning provides more headroom for both the voltage drop at a load step and the voltage increase at a load throw-off, thereby improving load-transient behavior.

At light loads, in which the converters operate in PFM mode, the typical output-voltage regulation is 1% higher than the nominal value. In the event of a load transient from light load to heavy load, the output voltage drops until it reaches the skip-comparator-low threshold, set to 1% below the nominal value, and enters PWM mode. During a release from heavy load to light load, active regulation turning on the N-channel switch minimizes the voltage overshoot.

TPS65051-Q1 volt_pos_lvs710.gif Figure 6. Dynamic Voltage Positioning

7.3.5 Soft Start

The two converters have an internal soft-start circuit that limits the inrush current during start-up. During soft start, control of the output-voltage ramp-up is as shown in Figure 7.

TPS65051-Q1 soft_start_lvs710.gif Figure 7. Soft Start

7.3.6 100% Duty-Cycle Low-Dropout Operation

The converters offer a low input-to-output voltage difference while still maintaining operation with the use of the 100% duty-cycle mode. In this mode, the P-channel switch is constantly on. This operational mode is useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range, (that is, the minimum input voltage to maintain regulation depends on the load current and output voltage) and can be calculated as:

Equation 1. TPS65051-Q1 eq_vin_lvs710.gif

where

  • IO max = maximum output current plus inductor ripple current
  • rDS(on) max = maximum P-channel switch rDS(on)
  • RL = dc resistance of the inductor
  • VO (max) = nominal output voltage plus maximum output-voltage tolerance

7.3.7 Undervoltage Lockout

The undervoltage-lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery, and disables all internal circuitry. The undervoltage-lockout threshold, sensed at the VCC pin, is typically 1.8 V, maximum 2 V.

7.3.8 Mode Selection

The MODE pin allows mode selection between forced PWM mode and power-save mode for both converters. Connecting this pin to GND enables the automatic PWM and power-save mode of operation. The converters operate in fixed-frequency PWM mode at moderate-to-heavy loads and in the PFM mode during light loads, maintaining high efficiency over a wide load-current range.

Pulling the MODE pin high forces both converters to operate constantly in the PWM mode even at light load currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power-save mode during light loads. For additional flexibility, it is possible to switch from power-save mode to forced-PWM mode during operation. This allows efficient power management by adjusting the operation of the converters to the specific system requirements.

7.3.9 Enable

To start up each converter independently, the device has a separate enable pin for each DC-DC converter and for each LDO. If EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3, or EN_LDO4 is set to high, the corresponding converter starts up with soft start as previously described.

Pulling the enable pin low forces the device into shutdown, with a shutdown quiescent current as defined in the electrical characteristics. In this mode, the P- and N-Channel MOSFETs turn off, and the entire internal control circuitry switches off. If disabled, internal 350-Ω resistors pull the outputs of the LDOs low, actively discharging the output capacitor. Proper operation requires termination of the enable pins. Do not leave them unconnected.

7.3.10 RESET

The device contains circuitry that can generate a reset pulse for a processor with a 100-ms delay time. The device senses the input voltage for a comparator at the THRESHOLD pin. When the voltage exceeds the threshold, the output goes high with a 100-ms delay time. An external resistor connected to the HYSTERESIS input defines the hysteresis. This circuitry is functional as soon as the supply voltage at VCC exceeds the undervoltage-lockout threshold. The TPS65051-Q1 device has a shutdown current (all DC-DC converters and LDOs are off) of 9 μA.

TPS65051-Q1 reset_lvs710.gif Figure 8. RESET Pulse Circuit

7.3.11 Short-Circuit Protection

All outputs are short-circuit protected with a maximum output current as defined in the Electrical Characteristics.

7.3.12 Thermal Shutdown

As soon as the junction temperature, TJ, exceeds 150°C (typically) for the DC-DC converters, the device goes into thermal shutdown. In this mode, the P- and N-channel MOSFETs turn off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis again. A thermal shutdown for one of the DC-DC converters disables both converters simultaneously.

The thermal shutdown temperature for the LDOs is typically 140°C. Therefore, an LDO used to power an external voltage never heats up the chip high enough to turn off the DC-DC converters. If one LDO exceeds the thermal shutdown temperature, all LDOs turn off simultaneously.

7.3.13 Low Dropout Voltage Regulators

The design of the low-dropout voltage regulators allows them to operate well with small ceramic input and output capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 400 mV (LDO1) and 280 mV (LDO2, LDO3, and LDO4) at rated output current. Each LDO supports a current-limit feature. The EN_LDO1, ENLDO2, EN_LDO3, and EN_LDO4 pins enable the LDOs. The use of external resistor dividers sets the output voltage of the LDOs.

7.4 Device Functional Modes

7.4.1 Power-Save Mode

The TPS65051-Q1 device is either in the ON or the OFF mode. The OFF mode is entered when the voltage on VCC is below the UVLO threshold of 1.8 V (typically). When the voltage at the VCC pin is higher than UVLO, the device enters ON mode. In the ON mode, the converters and LDOs are available for use.

Setting the MODE pin to 0 enables the power-save mode. If the load current decreases, the converters enter the power-save mode of operation automatically. During power-save mode, the converters operate with reduced switching frequency in PFM mode, and with a minimum quiescent current to maintain high efficiency. The converters position the output voltage 1% above the nominal output voltage. This voltage-positioning feature minimizes voltage drops caused by a sudden load step.

To optimize the converter efficiency at light load, the TPS65051-Q1 device monitors average current. If in PWM mode, the inductor current remains below a certain threshold, then the device enters power-save mode. Use Equation 2 to calculate the average output current threshold to enter PFM mode. Use Equation 3 to calculate the average output current threshold to leave PFM mode.

Equation 2. TPS65051-Q1 eq_ipfm_lvs710.gif
Equation 3. TPS65051-Q1 eq_ipsm_lvs710.gif

During power-save mode, a comparator monitors the output voltage. As the output voltage falls below the skip-comparator (skip comp) threshold, the P-channel switch turns on, and the converter effectively delivers a constant current. If the load is below the delivered current, the output voltage rises until it crosses the skip comp threshold again; then all switching activity ceases, reducing the quiescent current to a minimum until the output voltage has dropped below the threshold. If the load current is greater than the delivered current, the output voltage falls until it crosses the skip-comparator-low (skip comp low) threshold set to 1% below nominal VO; then the device exits power-save mode, and the converter returns to the PWM mode.

These control methods reduce the quiescent current to 12 μA per converter and the switching frequency to a minimum, achieving the highest converter efficiency. The PFM mode operates with low output-voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor; increasing capacitor value decreases the output ripple voltage.

Disable the power-save mode by driving the MODE pin high. In forced-PWM mode, both converters operate with fixed-frequency PWM mode regardless of the load.