SLVSCW2A September   2015  – February 2016 TPS657095

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  State Diagram
      2. 7.3.2  Power-up Timing
      3. 7.3.3  GPO
      4. 7.3.4  GPIO
      5. 7.3.5  LED_EN
      6. 7.3.6  PWM Dimming
      7. 7.3.7  Crystal Oscillator and CLKOUT
      8. 7.3.8  LDOs
      9. 7.3.9  Undervoltage Lockout
      10. 7.3.10 Power Up/Power Down Default States
      11. 7.3.11 Output Voltage Discharge for LDO1 and LDO2
      12. 7.3.12 Power-Good Status Bits for LDO1 and LDO2
      13. 7.3.13 Short-Circuit Protection
      14. 7.3.14 Thermal Shutdown
      15. 7.3.15 LED Driver
      16. 7.3.16 4kByte OTP Memory
        1. 7.3.16.1 Programming the 4KByte OTP Memory
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Operational Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
    6. 7.6 Register Map
      1. 7.6.1  DEV_AND_REV_ID Register Address: 00h
      2. 7.6.2  OTP_REV Register Address: 01h
      3. 7.6.3  GPIO_CTRL Register Address: 02h
      4. 7.6.4  PWM_OSC_CNTRL Register Address: 03h
      5. 7.6.5  ISINK_CURRENT Register Address: 04h
      6. 7.6.6  LDO_CTRL Register Address: 05h
      7. 7.6.7  LDO1_VCTRL Register Address: 06h
      8. 7.6.8  LDO2_VCTRL Register Address: 07h
      9. 7.6.9  PWM_DUTY_THR_L Register Address: 08h
      10. 7.6.10 PWM_DUTY_THR_H Register Address: 09h
      11. 7.6.11 RESERVED Register Address: 0Ah
      12. 7.6.12 PWM_DUTY_L Register Address: 0Bh
      13. 7.6.13 PWM_DUTY_H Register Address: 0Ch
      14. 7.6.14 RESERVED Register Address: 0Dh
      15. 7.6.15 SPARE Register Address: 0Eh
      16. 7.6.16 4K_OTP_PASSWORD Register Address: 0Fh
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Capacitor Selection
        2. 8.2.2.2 Input Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Summary
    2. 12.2 Chip Scale Package Dimensions

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The target application for the TPS657095 device is powering an embedded camera module.

8.2 Typical Application

TPS657095 App_schem_tps.gif Figure 30. Application Schematic

8.2.1 Design Requirements

Table 18. Design Parameters

DESIGN PARAMETER VALUE
Typical Input Voltage 5V
LDO1 Output Voltage 1.8V (off by default)
LDO2 Output Voltage 1.2V (off by default)

8.2.2 Detailed Design Procedure

8.2.2.1 Output Capacitor Selection

The control loop of the LDOs is internally compensated such that they operate with small ceramic output capacitors of 2.2µF.

8.2.2.2 Input Capacitor Selection

A low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits. The LDOs need a ceramic input capacitor with a minimum capacitance of 1.0µF. The input capacitor can be increased without any limit for better input voltage filtering.

Table 19. Tested Capacitors

TYPE VALUE VOLTAGE RATING SIZE SUPPLIER MATERIAL
GRM155R60J225ME15D 2.2 µF 6.3 V 0402 Murata Ceramic X5R
GRM185R60J225 2.2 µF 6.3 V 0603 Murata Ceramic X5R
GRM185R60J105K 1 µF 6.3 V 0603 Murata Ceramic X5R

8.2.3 Application Curves

The graphs below were taken using the TPS657095EVM with the passive components as listed below:

  • CIN(VCC) = GRM185R60J105K (1 µF / 6.3V)
  • COUT(LDO1) = COUT(LDO2) = GRM185R60J225 (2.2 µF / 6.3 V)
  • VCC = 5 V unless otherwise noted

Table 20. Table of Graphs

DESCRIPTION FIGURE
Line Transient Response LDO1 VCC = 3.6V to 5V to 3.6V; IOUT = 75mA; VOUT = 1.8V Figure 31
Line Transient Response LDO2 VCC = 3.6V to 5V to 3.6V; IOUT = 75mA; VOUT = 2.8V Figure 32
Load Transient Response LDO1 VCC = 5V; IOUT = 7.5mA to 68mA to 7.5mA;
VOUT = 1.8V		 Figure 33
Load Transient Response LDO2 VCC = 5V; IOUT = 7.5mA to 68mA to 7.5mA; VOUT = 2.8V Figure 34
LDO1 and LDO2 Start-up Timing VCC = 5V; IOUT = 0mA Figure 35
LDO1 and LDO2 Start-up Timing VCC = 5V; IOUT = 75mA Figure 36
Duty Cycle on CLKout vs Programmed Frequency VCC = 5V; f(crystal) = 24MHz; VLDO1 = 1.8V Figure 37
Period Jitter on CLKout vs Temperature and Output Frequency VCC = 5V; f(crystal) = 24MHz; VLDO1 = 1.8V Figure 38
TPS657095 LDO1_LineT.gif
Figure 31. Line Transient Response LDO1
TPS657095 LDO1_loadT.gif
Figure 33. Load Transient Response LDO1
TPS657095 LDO1_startup_W.gif
Figure 35. LDO1 Start-up Timing
TPS657095 D005_SLVSCW2.gif
VCC = 5 V, VLDO1 = 1.8 V, fCrystal = 24 MHz
Figure 37. Duty Cycle
TPS657095 LDO2_LineT.gif
Figure 32. Line Transient Response LDO2
TPS657095 LDO2_LoadT.gif
Figure 34. Load Transient Response LDO2
TPS657095 LDO2_Startup_W.gif
Figure 36. LDO2 Start-up Timing
TPS657095 D006_SLVSCW2.gif
VCC = 5 V
Figure 38. Period Jitter