SWCS106F March   2013  – July 2016 TPS659119-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Characteristics
    5. 7.5  External Component Recommendation
    6. 7.6  I/O Pullup and Pulldown Characteristics
    7. 7.7  Digital I/O Voltage Electrical Characteristics
    8. 7.8  I2C Interface and Control Signals
    9. 7.9  Switching Characteristics—I2C Interface and Control Signals
    10. 7.10 Power Consumption
    11. 7.11 Power References and Thresholds
    12. 7.12 Thermal Monitoring and Shutdown
    13. 7.13 32-kHz RTC Clock
    14. 7.14 VRTC LDO
    15. 7.15 VIO SMPS
    16. 7.16 VDD1 SMPS
    17. 7.17 VDD2 SMPS
    18. 7.18 EXTCTRL
    19. 7.19 LDO1 AND LDO2
    20. 7.20 LDO3 and LDO4
    21. 7.21 LDO5
    22. 7.22 LDO6 and LDO7
    23. 7.23 LDO8
    24. 7.24 Timing Requirements for Boot Sequence Example
    25. 7.25 Power Control Timing Requirements
    26. 7.26 Device SLEEP State Control Timing Requirements
    27. 7.27 Supplies State Control Through EN1 and EN2 Timing Characteristics
    28. 7.28 VDD1 Supply Voltage Control Through EN1 Timing Requirements
    29. 7.29 Typical Characteristics
      1. 7.29.1 VIO SMPS Curves
      2. 7.29.2 VDD1 SMPS Curves
      3. 7.29.3 VDD2 SMPS Curves
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Reference
      2. 8.3.2 Power Resources
      3. 8.3.3 PWM and LED Generators
      4. 8.3.4 Dynamic-Voltage Frequency Scaling and Adaptive-Voltage Scaling Operation
      5. 8.3.5 32-kHz RTC Clock
      6. 8.3.6 Real-Time Clock (RTC)
      7. 8.3.7 Thermal Monitoring and Shutdown
      8. 8.3.8 Crystal Oscillator Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Embedded Power Controller
        1. 8.4.1.1 State-Machine
          1. 8.4.1.1.1 Device POWER-ON Enable Conditions
          2. 8.4.1.1.2 Device POWER ON Disable Conditions
          3. 8.4.1.1.3 Device SLEEP Enable Conditions
          4. 8.4.1.1.4 Device Reset Scenarios
        2. 8.4.1.2 Boot Configuration and Switch-On and Switch-Off Sequences
        3. 8.4.1.3 Control Signals
          1. 8.4.1.3.1  SLEEP
          2. 8.4.1.3.2  PWRHOLD
          3. 8.4.1.3.3  BOOT1
          4. 8.4.1.3.4  NRESPWRON, NRESPWRON2
          5. 8.4.1.3.5  CLK32KOUT
          6. 8.4.1.3.6  PWRON
          7. 8.4.1.3.7  INT1
          8. 8.4.1.3.8  EN2 and EN1
          9. 8.4.1.3.9  GPIO0-8
          10. 8.4.1.3.10 HDRST Input
          11. 8.4.1.3.11 PWRDN
          12. 8.4.1.3.12 Watchdog
          13. 8.4.1.3.13 Tracking LDO
    5. 8.5 Programming
      1. 8.5.1 Time-Calendar Registers
      2. 8.5.2 General Registers
      3. 8.5.3 Compensation Registers
      4. 8.5.4 Backup Registers
      5. 8.5.5 I2C Interface
        1. 8.5.5.1 Addressing
        2. 8.5.5.2 Access Protocols
          1. 8.5.5.2.1 Single-Byte Access
          2. 8.5.5.2.2 Multiple-Byte Access To Several Adjacent Registers
      6. 8.5.6 Interrupts
    6. 8.6 Register Maps
      1. 8.6.1 Functional Registers
      2. 8.6.2 TPS659119-Q1_FUNC_REG Register Mapping Summary
      3. 8.6.3 TPS659119-Q1_FUNC_REG Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Step-down Converter Input Capacitors
        2. 9.2.2.2 Step-down Converter Output Capacitors
        3. 9.2.2.3 Step-down Converter Inductors
        4. 9.2.2.4 LDO Input Capacitors
        5. 9.2.2.5 LDO Output Capacitors
        6. 9.2.2.6 VCC7
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The TPS659119-Q1 device is an integrated power-management integrated-circuit (PMIC) available in an 80-pin, 0,5-mm pitch HTQFP package with thermal pad. This device is designed for automotive applications. The device provides three step-down converters and an interface to control an external converter. The device also provides eight LDOs, nine configurable GPIOs, two LED pulse generators, one PWM generator, and programmability for supporting different processors and applications.

The three step-down converters in this device are high-frequency switch-mode converters with integrated FETs. The converters are capable of synchronizing to an external clock input and support switching frequency between 2.7 MHz and 3.3 MHz. Two of the step-down converters support dynamic voltage scaling by a dedicated I2C interface for optimum power savings. The third converter can provide power for system I/Os, memory modules, or both which provides four programmable output-voltage settings.

The device includes eight general-purpose LDOs providing a wide range of voltage and current capabilities. Five of the LDOs support 1 to 3.3 V with 100-mV step and three (LDO1, LDO2, LDO4) of the LDOs support 1 to 3.3 V with 50-mV step. All LDOs are fully controllable by the I2C interface and are supplied from either a system supply or a pre-regulated supply.

The power-up and power-down controller is configurable and programmable through EEPROM. The TPS659119-Q1 devices include a 32-kHz RC oscillator to sequence all resources during power up and power down. In cases where a fast start up is needed, a 16-MHz crystal oscillator is also included to quickly generate a stable 32-kHz for the system. The device also includes an RTC module that provides date, time, calendar, and alarm capability. The RTC module is best used when a 16-MHz crystal or an external and high accuracy 32-kHz clock is present.

The TPS659119-Q1 device also includes nine configurable GPIOs with a multiplexed feature. Four of the GPIOs can be configured and used as enable signals for external resources, which can be included in the power-up and power-down sequence. Two of the GPIOs have a 10-mA current-sink capability for driving external LEDs. The device also includes two on and two off LED-pulse generators and one PWM generator with programmable frequency and duty cycle.

8.2 Functional Block Diagram

TPS659119-Q1 fbd_swcs106.gif Figure 14. Top-Level Diagram

8.3 Feature Description

8.3.1 Power Reference

The bandgap voltage reference is filtered by using an external capacitor connected across the VREF output and the analog ground, REFGND (see the Recommended Operating Conditions section). The VREF voltage is distributed and buffered inside the device.

8.3.2 Power Resources

The power resources provided by the TPS659119-Q1 device include inductor-based switched-mode power supplies (SMPSs) and linear low-dropout voltage regulators (LDOs). These supply resources provide the required power to the external processor cores and external components, and to modules embedded in the TPS659119-Q1 device.

Two of the integrated SMPSs and the external SMPS controller (EXTCTRL) have voltage scaling capability. These SMPSs provide independent core-voltage domains to the host processor. When changing the output voltage, VDD1 and VDD2 reach the new value through successive steps of 2.5 to 12.5 mV. The size of the voltage step is selected by the TSTEP bit. With a 0.8-V reference, EXTCTRL has a target slew rate of 100 mV / 20 μs. Use Equation 1 to calculate new output values which are reached in successive smaller steps.

Equation 1. N × LSB

where

  • LSB = 16.7 mV
  • N = 1 to 4

A suitable combination of steps is calculated internally based on the current and new target values for the output voltage.

The VIO SMPS provides a supply voltage for the host processor I/Os.

Table 1 lists the power sources provided by the TPS659119-Q1 device.

Table 1. Power Sources

RESOURCE TYPE VOLTAGES POWER
VIO SMPS 1.5, 1.8, 2.5, and 3.3 V 1500 mA
VDD1 SMPS 0.6 to 1.5 V in 12.5-mV steps 1500 mA
Programmable-multiplication factor: x2, x3
VDD2 SMPS 0.6 to 1.5 V in 12.5-mV steps 1500 mA
Programmable-multiplication factor: x2, x3
LDO1 LDO 1 to 3.3 V, 0.05-V step 320 mA
LDO2 LDO 1 to 3.3 V, 0.05-V step 320 mA
LDO3 LDO 1 to 3.3 V, 0.1-V step 200 mA
LDO4 LDO 1 to 3.3 V, 0.05-V step 50 mA
LDO5 LDO 1 to 3.3 V, 0.1-V step 300 mA
LDO6 LDO 1 to 3.3 V, 0.1-V step 300 mA
LDO7 LDO 1 to 3.3 V, 0.1-V step 300 mA
LDO8 LDO 1 to 3.3 V, 0.1-V step 300 mA

8.3.3 PWM and LED Generators

The TPS659119-Q1 device has two LED ON and OFF signal generators, LED1 and LED2. The LED1 and LED2 signals have independently controllable periods from 125 ms to 8 s and an ON time from 62.5 to 500 ms. Within the period, one or two ON pulses can be generated (control bit LED1(2)_SEQ). The user must take care to program the period and ON time correctly because no limitation on selected values is imposed. The LED1 and LED2 signals can be routed to GPIO1 and GPO3 open-drain outputs, respectively. These GPIOs have a current-sink capability of 10 mA.

The PWM generator frequency and duty cycle are set by the PWM_FREQ and PWM_DUTY_CYCLE bits, respectively. The PWM generator signal can be connected to the GPIO3 or GPIO8 output. The PWM generator uses the 3-MHz clock, which is not available in off mode. To enable the PWM in sleep mode, the I2CHS_KEEPON bit must be set to 1.

8.3.4 Dynamic-Voltage Frequency Scaling and Adaptive-Voltage Scaling Operation

    Dynamic-voltage frequency scaling (DVFS) operation A supply voltage value corresponding to a targeted frequency of the digital core supplied is programmed in VDD1_OP_REG or VDD2_OP_REG registers. The slew rate of the voltage supply reaching a new VDD1_OP_REG or VDD2_OP_REG programmed value is limited to 12.5 mV/µs, fixed value.
    Adaptative-voltage scaling (AVS) operation A supply voltage value corresponding to a supply voltage adjustment is programmed in VDD1_SR_REG or VDD2_SR_REG registers. The supply voltage is then tuned by the digital core supplied, based its performance self-evaluation. The slew rate of VDD1 or VDD2 voltage supply reaching a new programmed value is programmable though the VDD1_REG or VDD2_REG register, respectively.

A serial control interface (optional mode for EN1 and EN2 pins) can be dedicated to voltage scaling applications in order to provide dedicated access to the VDD1_OP_REG, VDD1_SR_REG and VDD2_OP_REG, VDD2_SR_REG registers.

A general-purpose serial-control interface (CTL-I2C) also gives access to these registers if the SR_CTL_I2C_SEL control bit is set to 1 in the DEVCTRL_REG register (default inactive).

Both control interfaces are compliant with HS-I2C specification (100 Kbps, 400 Kbps, or 3.4 Mbps).

8.3.5 32-kHz RTC Clock

The TPS659119-Q1 device can provide a 32-kHz clock to the platform through the CLK32KOUT output. Selection of the default RTC clock source is controlled by the EEPROM bit CK32K_CTRL in the DEVCTRL_REG register. This clock must be present for any state of the EPC except the NO SUPPLY state. The following lists the three possible sources for this clock.

    Crystal Oscillator To use the crystal oscillator, a 16.384-MHz crystal should be placed between the OSC16MIN and OSC16MOUT pins. The OSCEXT32K pin should be grounded. The 32-kHz clock is produced by dividing the crystal oscillator output by 500. A higher-frequency crystal is used to accelerate the start-up time of the device. Figure 15 shows an essential schematic of the oscillator .
    External Clock Source An external 32-kHz clock source may be used by grounding the OSC16MIN pin, floating the OSC16MOUT pin, and applying the clock to the OSCEXT32K pin. When four clock edges are counted on the OSCEXT32K pin, an internal clock-selection MUX selects the external clock source rather than the crystal oscillator. A means of switching between the crystal oscillator and the external clock source is not included in the design. Either one or the other can be used in a given application, but not both.
    Internal RC Oscillator Depending on the state of the CK32K_CTRL bit, an internal 32-kHz RC oscillator can also be used as the clock source for the RTC if an accurate time-base is not required.
TPS659119-Q1 cry_osc_wcs062.gif Figure 15. 16-MHz Crystal Oscillator

8.3.6 Real-Time Clock (RTC)

The RTC, which is driven by the 32-kHz clock, provides the alarm and timekeeping functions. The RTC remains supplied when the device is in the OFF or the BACKUP state.

The main functions of the RTC block are:

  • Time information (seconds, minutes, and hours) directly in binary-coded decimal (BCD) format
  • Calendar information (day, month, year, and day of the week) directly in BCD code up to year 2099
  • Programmable interrupts generation
    • The RTC can generate two interrupts: a timer interrupt RTC_PERIOD_IT periodically (1-s, 1-m, 1-h, and 1-d period) and an alarm interrupt RTC_ALARM_IT at a precise time of the day (alarm function). These interrupts are enabled using IT_ALARM and IT_TIMER control bits. Periodically, interrupts can be masked during the SLEEP period to avoid host interruption and are automatically unmasked after SLEEP wakeup (using the IT_SLEEP_MASK_EN control bit).
  • Oscillator frequency calibration and time correction

TPS659119-Q1 SWCS049-015.gif Figure 16. RTC Digital Section Block Diagram

8.3.7 Thermal Monitoring and Shutdown

A thermal-protection module monitors the junction temperature of the device versus two thresholds:

  • Hot-die temperature threshold
  • Thermal-shutdown temperature threshold

When the hot-die temperature threshold is reached, an interrupt is sent to software to close the noncritical running tasks.

When the thermal-shutdown temperature threshold is reached, the TPS659119-Q1 device is set under reset and a transition to the OFF state initiates. Then the POWER-ON enable conditions of the device are not considered until the die temperature has decreased below the hot-die threshold. Hysteresis is applied to the hot-die and shutdown thresholds when detecting a falling edge of temperature and both detections are debounced to avoid any parasitic detection.

The TPS659119-Q1 device allows programming of four hot-die temperature thresholds to increase the flexibility of the system.

By default, the thermal protection is enabled in ACTIVE state, but can be disabled through programming the THERM_REG register. The thermal protection can be enabled in the SLEEP state programming the SLEEP_KEEP_RES_ON register. The thermal protection is automatically enabled during an OFF-to-ACTIVE state transition and is kept enabled in the OFF state after a switch-off sequence caused by a thermal shutdown event. A transition to the OFF-state sequence caused by thermal shutdown event is highlighted in Table 67 (the INT_STS_REG status register). Recovery from this OFF state is initiated (switch-on sequence) when the die temperature falls below the hot-die temperature threshold.

Hot-die and thermal shutdown temperature threshold detection states can be monitored or masked by reading or programming the THERM_REG register. Programming the INT_MSK_REG register can mask the hot-die interrupt.

8.3.8 Crystal Oscillator Power-On Reset

The crystal oscillator uses a local independent power-on-reset (POR) circuit. If the crystal oscillator or external clock input are used, then VCC7 must be higher than the rising threshold of this POR circuit (3.96 V max). If VCC7 is not higher than the rising POR threshold, a clock is not delivered to the digital core inside the PMIC and the device does not power up.

8.4 Device Functional Modes

8.4.1 Embedded Power Controller

The embedded power controller (EPC) manages the state of the device and controls the power-up sequence.

8.4.1.1 State-Machine

The EPC supports the following states:

  • NO SUPPLY: The main battery-supply voltage is not high enough to power the VRTC regulator. A global reset is asserted in this case. The device is turned off completely.
  • OFF: The main battery-supply voltage is high enough to start the power-up sequence but device power-on is not enabled. All power supplies are in the OFF state except VRTC.
  • ACTIVE: Device POWER-ON enable conditions are met and regulated power supplies are on or can be enabled with full current-capability.
  • SLEEP: Device SLEEP-enable conditions are met and some selected regulated power supplies are in low-power mode.

Figure 17 shows the transitions for the state-machine.

TPS659119-Q1 embed_pwr_ctrl_state_mach_wcs062.gif

NOTE:

PWRHOLD enables power-on unless the pin is programmed as a GPI pin.
Figure 17. Embedded Power-Control State-Machine

8.4.1.1.1 Device POWER-ON Enable Conditions

The enable conditions of device POWER ON include the following:

  • None of the device POWER-ON disable conditions are met.
  • One of the following is met:
    • PWRON-signal low level
    • PWRHOLD signal high level
    • DEV_ON control bit set to 1 (default inactive)
    • Interrupt flag active (default INT1 low) generates a POWER ON enable condition during a fixed delay (tDOINT1 pulse duration defined in ). Interrupt sources expected (if enabled), when the device is off:
      • RTC alarm interrupt

The active interrupt flag generates a POWER-ON enable-condition pulse of length tDOINT1 only when the device is in the OFF state (when the NRESPWRON signal is low). The POWER-ON enable-condition pulse occurs only if the interrupt status bit is initially low (no previous interrupt pending in the status register). The interrupt status register must first be cleared to allow device power off during the tDOINT1 pulse duration.

The GPIO2 signal cannot be used to turn on the device, even if the associated interrupt is not masked. The GPIO0, GPIO1, GPIO3, GPIO4, or GPIO5 signals can be used to turn on the device, if the associated interrupt is not masked.

NOTE

The watchdog interrupt is not a power-on event, but it wakes up the device from sleep mode.

8.4.1.1.2 Device POWER ON Disable Conditions

The disable conditions of device POWER ON include one of the following:

  • PWRON signal low level during more than the long-press delay: PWON_LP_DELAY (can be disabled though register programming). The interrupt corresponding to this condition is PWRON_LP_IT in the INT_STS_REG register.
  • The die temperature reaches the thermal-shutdown threshold (THERM_TS = 1).
  • DEV_OFF or DEV_OFF_RST control bit is set to 1 (the DEV_OFF value is cleared when the device is in the OFF state).

NOTE

If the DEV_ON bit is set to 1, after switch-off, the device switches back on. To keep the device off, DEV_ON must be cleared first.

8.4.1.1.3 Device SLEEP Enable Conditions

The enable conditions of the device SLEEP state include all of the following:

  • SLEEP-signal low level (default, or high level depending on the programmed polarity)
  • DEV_SLP control bit is set to 1.
  • Interrupt flag inactive (default INT1 high): no nonmasked interrupt is pending.

The SLEEP state is controlled by programming DEV_SLP and keeping the SLEEP signal floating. This state is also controlled through the SLEEP signal by setting the DEV_SLP bit to 1 one time after device turn-on.

8.4.1.1.4 Device Reset Scenarios

The device has three reset scenarios:

    Full reset All digital logic of the device is reset.

    Caused by POR (power on reset) when VCC7 < VBNPR

    General reset No impact on the RTC, backup registers, or interrupt status.

    Caused by one of the follwoing:

    • PWON_LP_RST bit set high
    • DEV_OFF_RST bit set high
    • HDRST input set high

    Turnoff Power reinitialization in off or backup mode.

Table 7 lists a mapping of the digital registers to these reset scenarios.

8.4.1.2 Boot Configuration and Switch-On and Switch-Off Sequences

The power sequence is the automated switch-on of the devices resources when an OFF-to-ACTIVE transition occurs. The power-on sequence has 15 sequential time slots to which resources (DCDCs, LDOs, 32-kHz clock, GPIO0, GPIO2, GPIO6, GPIO7) are assigned. The selected length of the time slot is either 0.5 ms or 2 ms. If a resource is not assigned to any time slot, the resource is in OFF mode after the power-on sequence and the voltage level can be changed through the register SEL bits before enabling the resource.

A power-off disables all power resources at the same time by default. By setting the PWR_OFF_SEQ control bit to 1, power-off follows the power-up sequence in reverse order (the first resource powered on is the last resource powered off).

The values of VDD1, VDD2, and EXTCTRL set in the boot sequence can be selected from 16 steps. For the whole range, 100-mV steps are available: 0.6 V and 0.7 to 1.4 V and 1.5 V. From 0.8 to 1.4 V, additional values with 50-mV step resolution can be set: 0.85 V and 1.05 V to 1.35 V.

For LDO1, LDO2, and LDO4 all levels from 1 to 3.3 V are selectable in the boot sequence with 50-mV steps. For other LDOs, the level is selectable with 100-mV steps, from 1 to 3.3 V.

The device supports two boot configurations, which define the power sequence and several device control bits. The boot configuration is selectable by the device BOOT1 pin.

BOOT1 Boot Configuration
0 Fixed boot mode
1 EEPROM boot mode

The BOOT1 input pad is disabled after the boot mode is read at power up, to save power.

Table 2 and Table 3 list the power sequence and general control bits defined in the boot sequence, respectively.

Fixed boot mode is the same in all orderable devices while EEPROM boot mode is different in each. Table 2 lists the boot configuration for power sequence control bits and Table 3 lists the boot configuration for general control bits. Refer to Table 4 for EEPROM boot-mode descriptions for specific orderable devices.

Table 2. Boot Configuration: Power-Sequence Control Bits

REGISTER BIT DESCRIPTION TPS659119-Q1
FIXED BOOT EEPROM BOOT
VDD1_OP_REG/VDD1_SR_REG EXTCTRL ratio selection for boot. Levels available: 1.2 V x
0.6, 0.7, 0.8, 0.85, 0.9, 0.95 … 1.35, 1.4, and 1.5 V
VDD1_REG VGAIN_SEL VDD1 gain selection, x1 or x2 x1 x
EEPROM VDD1 time slot selection 3 x
DCDCCTRL_REG VDD1_PSKIP VDD1 pulse skip mode enable Enable skip x
VDD2_OP_REG/VDD2_SR_REG VDD2 voltage level selection for boot. Levels available: 1.5 V x
0.6, 0.7, 0.8, 0.85, 0.9 … 0.95 to 1.35, 1.4, and 1.5 V
VDD2_REG VGAIN_SEL VDD2 gain selection, x1 or x3 x1 x
EEPROM VDD2 time slot selection 6 x
DCDCCTRL_REG VDD2_PSKIP VDD2 pulse skip mode enable Enable skip x
VIO_REG SEL[3:2] VIO voltage selection 1.8 V x
EEPROM VIO time slot selection 4 x
DCDCCTRL_REG VIO_PSKIP VIO pulse skip mode enable Enable skip x
EXTCTRL_OP_REG/EXTCTRL_SR_REG EXTCTRL voltage level selection for boot. Levels available include: Off x
SEL[6:0] = 3, 11, 19, 23, 27, … 59, 63, 67
Where: Ratio = 48 / (45 + SEL[6:0])
EEPROM EXTCTRL time slot selection Off x
LDO1_REG SEL[7:2] LDO1 voltage selection 1.05 V x
EEPROM LDO1 time slot Off x
LDO2_REG SEL[7:2] LDO2 voltage selection 1.2 V x
EEPROM LDO2 time slot 7 x
LDO3_REG SEL[6:2] LDO3 voltage selection LDO3 voltage: 1 V x
EEPROM LDO3 time slot Off x
LDO4_REG SEL[7:2] LDO4 voltage selection 1.2 V x
EEPROM LDO4 time slot 2 x
LDO5_REG SEL[6:2] LDO5 voltage selection LDO5 voltage: 1 V x
EEPROM LDO5 time slot Off x
LDO6_REG SEL[6:2] LDO6 voltage selection LDO6 voltage: 1 V x
EEPROM LDO6 time slot Off x
LDO7_REG SEL[6:2] LDO7 voltage selection 1.2 V x
EEPROM LDO7 time slot 5 x
LDO8_REG SEL[6:2] LDO8 voltage selection 1 V x
EEPROM LDO8 time slot 7 x
CLK32KOUT pin CLK32KOUT time slot 5 x
NRESPWRON, NRESPWRON2 pin NRESPWRON time slot 10 x
GPIO0 pin GPIO0 time slot 1 x
GPIO2 pin GPIO2 time slot Off x
GPIO6 pin GPIO6 time slot 6 x
GPIO7 pin GPIO7 time slot 5 x

Table 3. Boot Configuration: General Control Bits

REGISTER BIT DESCRIPTION TPS659119-Q1
FIXED BOOT EEPROM BOOT
VRTC_REG VRTC_OFFMASK 0: VRTC LDO is in low-power mode during OFF state. 0 x
1: VRTC LDO is in full-power mode during OFF state.
DEVCTRL_REG CK32K_CTRL 0: Clock source is crystal / external clock. Crystal x
1: Clock source is internal RC oscillator.
DEVCTRL_REG DEV_ON 0: No impact 0 x
1: Maintains device on, in ACTIVE or SLEEP state
DEVCTRL2_REG TSLOTD Boot sequence time slot duration: 2 ms x
0: 0.5 ms
1: 2 ms
DEVCTRL2_REG PWON_LP_OFF 0: Turn off device after PWRON long-press not allowed. 1 x
1: Turn off device after PWRON long-press.
DEVCTRL2_REG PWON_LP_RST 0: No impact 1 x
1: Reset digital core when device is off
DEVCTRL2_REG IT_POL 0: INT1 signal is active-low. 0 x
1: INT1 signal is active-high.
INT_MSK_REG VMBHI_IT_MSK 0: Device automatically switches on at NO SUPPLY-to-OFF or BACKUP-to-OFF transition 1 x
1: Start-up reason required before switch-on
INT_MSK3_REG GPIO5_F_IT_MSK 0: GPIO5 falling-edge detection interrupt not masked 1 x
1: GPIO5 falling-edge detection interrupt masked
INT_MSK3_REG GPIO5_R_IT_MSK 0: GPIO5 rising-edge detection interrupt not masked 0 x
1: GPIO5 rising-edge detection interrupt masked
INT_MSK3_REG GPIO4_F_IT_MSK 0: GPIO4 falling-edge detection interrupt not masked 1 x
1: GPIO4 falling-edge detection interrupt masked
INT_MSK3_REG GPIO4_R_IT_MSK 0: GPIO4 rising-edge detection interrupt not masked 0 x
1: GPIO4 rising-edge detection interrupt masked
GPIO0_REG GPIO_ODEN 0: GPIO0 configured as push-pull output Push-pull x
1: GPIO0 configured as open-drain output
WATCHDOG_REG WATCHDOG_EN 0: Watchdog disabled 1 x
1: Watchdog enabled, periodic operation with 100 s
VMBCH_REG VMBBUF_BYPASS 0: Enable input buffer for external resistive divider Disable buffer x
1: In single-cell system, disable buffer for low lower
BOOTSEQVER_REG BOOTSEQVER_SEL EEPROM boot sequence version number 0x20 x
EEPROM AUTODEV_ON 0: PWRHOLD pin is used as PWRHOLD feature. 1, PWRHOLD pin is GPI x
1: PWRHOLD pin is GPI. After power on, DEV_ON set high internally, no processor action needed to maintain supplies.
EEPROM PWRDN_POL 0: PWRDN signal is active-low. Active-low x
1: PWRDN signal is active-high.

Table 4. EEPROM Configuration

BOOTSEQVER: BOOTSEQVER_
REG
= 0x24		 BOOTSEQVER_
REG
= 0x26		 BOOTSEQVER_
REG
= 0x30		 BOOTSEQVER_
REG
= 0x20		 BOOTSEQVER_
REG
= 0x28		 BOOTSEQVER_
REG
= 0x2A		 BOOTSEQVER_
REG
= 0x22		 BOOTSEQVER_REG
= 0x1C		 BOOTSEQVER_
REG
= 0x1A
ORDERABLE DEVICE NUMBER: TPS659119AIPFP
RQ1		 TPS659119CAIPFP
RQ1		 TPS659119BAIPFP
RQ1		 TPS659119DAIPFP
RQ1		 TPS659119EAIPFP
RQ1		 TPS659119FAIPFP
RQ1		 TPS659119HAIPFP
RQ1		 TPS659119KBIPFP
RQ1		 TPS659119LBIPFP
RQ1
VDD1_SLOT Slot 15 Slot 12 Slot 11 OFF Slot 15 Slot 15 OFF Slot 15 OFF
VDD2_SLOT Slot 8 Slot 4 Slot 12 Slot 8 Slot 8 Slot 8 Slot 8 Slot 8 Slot 8
VIO_SLOT Slot 3 Slot 4 Slot 7 Slot 3 Slot 3 Slot 3 Slot 3 Slot 3 Slot 3
EXTCTRL_SLOT Slot 1 Slot 3 Slot 10 Slot 1 Slot 1 Slot 1 Slot 1 Slot 1 Slot 1
VDIG1_SLOT (LDO1) Slot 15 Slot 5 Slot 5 OFF Slot 15 Slot 15 OFF Slot 15 OFF
VDIG2_SLOT (LDO2) Slot 6 Slot 5 Slot 4 Slot 5 Slot 6 Slot 6 Slot 6 Slot 6 Slot 6
VDAC_SLOT (LDO3) OFF Slot 2 Slot 6 OFF OFF Slot 3 OFF Slot 3 OFF
VPLL_SLOT (LDO4) OFF Slot 5 Slot 4 Slot 1 OFF Slot 1 Slot 1 Slot 1 Slot 1
VAUX1_SLOT (LDO5) Slot 11 OFF Slot 7 Slot 11 Slot 11 Slot 11 Slot 11 Slot 11 Slot 11
VMMC_SLOT (LDO6) Slot 7 Slot 13 Slot 6 Slot 7 Slot 7 Slot 7 Slot 7 Slot 7 Slot 7
VAUX33_SLOT (LDO7) Slot 12 Slot 6 Slot 8 Slot 12 Slot 12 Slot 12 Slot 12 Slot 12 Slot 12
VAUX2_SLOT (LDO8) OFF Slot 14 Slot 3 OFF OFF OFF OFF OFF OFF
GPIO0_SLOT Slot 5 Slot 1 Slot 9 Slot 6 Slot 5 Slot 5 Slot 5 Slot 5 Slot 5
GPIO2_SLOT OFF Slot 4 Slot 7 OFF OFF OFF OFF OFF OFF
GPIO6_SLOT OFF Slot 10 Slot 12 OFF OFF OFF Slot 15 OFF Slot 15
GPIO7_SLOT OFF OFF Slot 9 OFF OFF OFF Slot 15 OFF Slot 15
CLK32KOUT_SLOT Slot 10 Slot 7 Slot 11 Slot 10 Slot 10 Slot 10 Slot 10 Slot 10 Slot 10
NRESPWRON_SLOT Slot 14 Slot 10 Slot 14 Slot 14 Slot 14 Slot 14 Slot 14 Slot 14 Slot 14
VDD1_VSEL 1.05 V 1.05 V 1.2 V 1.05 V 1.05 V 1.05 V 1.05 V 1.05 V 1.05 V
VDD2_VSEL 1.5 V 1.5 V 1.2 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V
VIO_VSEL 1.8 V 1.8 V 3.3 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V
EXTCTRL_VSEL (Ratio) EXTCTRL Divider Ratio = 2/3 EXTCTRL Divider Ratio = 12/19 EXTCTRL Divider Ratio = 2/3 EXTCTRL Divider Ratio = 1/2 EXTCTRL Divider Ratio = 12/19 EXTCTRL Divider Ratio = 12/19 EXTCTRL Divider Ratio = 12/19 EXTCTRL Divider Ratio = 12/19 EXTCTRL Divider Ratio = 12/19
VDIG1_VSEL (LDO1) 1.05 V 1 V 1.8 V 1.05 V 1.05 V 1.05 V 1.05 V 1.05 V 1.05 V
VDIG2_VSEL (LDO2) 1.2 V 1.2 V 1.8 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V
VDAC_VSEL (LDO3) 1 V 1.2 V 3.3 V 1 V 1 V 1.8 V 1 V 1.8 V 1 V
VPLL_VSEL (LDO4) 0.8 V 1.8 V 1.8 V 1.25 V 0.8 V 1.2 V 1.2 V 1.2 V 1.2 V
VAUX1_VSEL (LDO5) 1 V 3.2 V 3.3 V 1 V 1 V 1 V 1 V 1 V 1 V
VMMC_VSEL (LDO6) 1.8 V 1.8 V 3.3 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V
VAUX33_VSEL (LDO7) 2.8 V 2.8 V 3.3 V 2.8 V 2.8 V 2.8 V 2.8 V 2.8 V 2.8 V
VAUX2_VSEL (LDO8) 1 V 2.8 V 1.8 V 1 V 1 V 1 V 1 V 1 V 1 V
VDD1_GAINSEL 1× 1× 1× 1× 1× 1× 1× 1× 1×
VDD2_GAINSEL 1× 1× 1× 1× 1× 1× 1× 1× 1×
VDD1_PSKIP VDD1 PFM mode enabled VDD1 in PWM mode only VDD1 in PWM mode only VDD1 PFM mode enabled VDD1 PFM mode enabled VDD1 PFM mode enabled VDD1 PFM mode enabled VDD1 PFM mode enabled VDD1 PFM mode enabled
VDD2_PSKIP VDD2 PFM mode enabled VDD2 in PWM mode only VDD2 in PWM mode only VDD2 PFM mode enabled VDD2 PFM mode enabled VDD2 PFM mode enabled VDD2 PFM mode enabled VDD2 PFM mode enabled VDD2 PFM mode enabled
VIO_PSKIP VIO PFM mode enabled VIO in PWM mode only VIO in PWM mode only VIO PFM mode enabled VIO PFM mode enabled VIO PFM mode enabled VIO PFM mode enabled VIO PFM mode enabled VIO PFM mode enabled
TSLOTD 0.5 ms 0.5 ms 2 ms 0.5 ms 0.5 ms 0.5 ms 0.5 ms 0.5 ms 0.5 ms
CLK32K_CTRL CLK32KOUT derived from XTAL oscillator CLK32KOUT derived from XTAL oscillator CLK32KOUT derived from XTAL oscillator CLK32KOUT derived from XTAL oscillator CLK32KOUT derived from XTAL oscillator CLK32KOUT derived from XTAL oscillator CLK32KOUT derived from XTAL oscillator CLK32KOUT derived from XTAL oscillator CLK32KOUT derived from XTAL oscillator
ITPOL INT1 output active-low INT1 output active-low INT1 output active-low INT1 output active-low INT1 output active-low INT1 output active-low INT1 output active-low INT1 output active-low INT1 output active-low
PWRDN_POL PWRDN input active-low PWRDN input active-low PWRDN input active-high PWRDN input active-low PWRDN input active-low PWRDN input active-low PWRDN input active-low PWRDN input active-low PWRDN input active-low
WATCHDOG Watchdog disabled Watchdog disabled Watchdog disabled Watchdog disabled Watchdog disabled Watchdog disabled Watchdog disabled Watchdog disabled Watchdog disabled
PWRON_LP_RST Digital core reset when device is OFF Digital core reset when device is OFF Digital core reset when device is OFF Digital core reset when device is OFF Digital core reset when device is OFF Digital core reset when device is OFF Digital core reset when device is OFF Digital core reset when device is OFF Digital core reset when device is OFF
GPIO0_ODEN GPIO0 is push-pull GPIO0 is push-pull GPIO0 is push-pull GPIO0 is push-pull GPIO0 is push-pull GPIO0 is push-pull GPIO0 is push-pull GPIO0 is push-pull GPIO0 is push-pull
GPIO5_R_IT_MSK GPIO5 rising-edge interrupt enabled GPIO5 rising-edge interrupt masked GPIO5 rising-edge interrupt masked GPIO5 rising-edge interrupt enabled GPIO5 rising-edge interrupt enabled GPIO5 rising-edge interrupt enabled GPIO5 rising-edge interrupt enabled GPIO5 rising-edge interrupt enabled GPIO5 rising-edge interrupt enabled
GPIO5_F_IT_MSK GPIO5 falling-edge interrupt masked GPIO5 falling-edge interrupt masked GPIO5 falling-edge interrupt masked GPIO5 falling-edge interrupt masked GPIO5 falling-edge interrupt masked GPIO5 falling-edge interrupt masked GPIO5 falling-edge interrupt masked GPIO5 falling-edge interrupt masked GPIO5 falling-edge interrupt masked
GPIO4_R_IT_MSK GPIO4 rising-edge interrupt enabled GPIO4 rising-edge interrupt masked GPIO4 rising-edge interrupt masked GPIO4 rising-edge interrupt enabled GPIO4 rising-edge interrupt enabled GPIO4 rising-edge interrupt enabled GPIO4 rising-edge interrupt enabled GPIO4 rising-edge interrupt enabled GPIO4 rising-edge interrupt enabled
GPIO4_F_IT_MSK GPIO4 falling-edge interrupt masked GPIO4 falling-edge interrupt masked GPIO4 falling-edge interrupt masked GPIO4 falling-edge interrupt masked GPIO4 falling-edge interrupt masked GPIO4 falling-edge interrupt masked GPIO4 falling-edge interrupt masked GPIO4 falling-edge interrupt masked GPIO4 falling-edge interrupt masked
VMBHI_IT_MSK VCCS > VMBHI is NOT a power-on enable condition VCCS > VMBHI is NOT a power-on enable condition VCCS > VMBHI is NOT a power-on enable condition VCCS > VMBHI is NOT a power-on enable condition VCCS > VMBHI is NOT a power-on enable condition VCCS > VMBHI is NOT a power-on enable condition VCCS > VMBHI is NOT a power-on enable condition VCCS > VMBHI is NOT a power-on enable condition VCCS > VMBHI is NOT a power-on enable condition
VMBBUF_BYPASS VCCS buffer disabled VCCS buffer disabled VCCS buffer disabled VCCS buffer disabled VCCS buffer disabled VCCS buffer disabled VCCS buffer disabled VCCS buffer disabled VCCS buffer disabled
AUTO_DEVON PWRHOLD pin keeps PMIC on PWRHOLD pin keeps PMIC on PWRHOLD pin keeps PMIC on PWRHOLD pin keeps PMIC on PWRHOLD pin keeps PMIC on PWRHOLD pin keeps PMIC on PWRHOLD pin keeps PMIC on PWRHOLD pin keeps PMIC on PWRHOLD pin keeps PMIC on
PWRON_LP_OFF PWRON long-press turnoff ENABLED PWRON long-press turnoff DISABLED PWRON long-press turnoff DISABLED PWRON long-press turnoff ENABLED PWRON long-press turnoff ENABLED PWRON long-press turnoff ENABLED PWRON long-press turnoff ENABLED PWRON long-press turnoff ENABLED PWRON long-press turnoff ENABLED
DEV_ON DEV_ON bit NOT set by default DEV_ON bit NOT set by default DEV_ON bit NOT set by default DEV_ON bit NOT set by default DEV_ON bit NOT set by default DEV_ON bit NOT set by default DEV_ON bit NOT set by default DEV_ON bit NOT set by default DEV_ON bit NOT set by default
VRTC_OFFMASK VRTC in low-power mode during OFF state VRTC in low-power mode during OFF state VRTC in low-power mode during OFF state VRTC in low-power mode during OFF state VRTC in low-power mode during OFF state VRTC in low-power mode during OFF state VRTC in full-power mode during OFF state VRTC in low-power mode during OFF state VRTC in full-power mode during OFF state

8.4.1.3 Control Signals

8.4.1.3.1 SLEEP

When none of the device SLEEP-disable conditions are met, a falling edge (default or rising edge, depending on the programmed polarity) of this signal causes an ACTIVE-to-SLEEP state transition of the device. A rising edge (default or falling edge, depending on the programmed polarity) causes a transition back to the ACTIVE state. This input signal is level-sensitive and no debouncing is applied.

While the device is in the SLEEP state, predefined resources are automatically set in the low-power mode or off. Resources can be kept in the active mode (full-load capability) by programming the SLEEP_KEEP_LDO_ON and the SLEEP_KEEP_RES_ON registers. These registers contain 1 bit per power resource. If the bit is set to 1, then that resource stays in active mode when the device is in the SLEEP state.

The CLK32KOUT pin is also included in the SLEEP_KEEP_RES_ON register and the 32-kHz clock output is maintained in the SLEEP state if the corresponding mask bit is set.

The status (low or high) of GPO0, GPO6, GPO7, and GPO8 is also controlled by the SLEEP signal, to allow enabling and disabling of external resources during sleep.

8.4.1.3.2 PWRHOLD

The PWRHOLD pin can be used as a PWRHOLD signal input or as a general purpose input (GPI). The mode is selected by the AUTODEV_ON bit, which is part of the boot configuration. When AUTODEV_MODE = 0, the PWRHOLD feature is selected.

Configured as PWRHOLD, when none of the device POWER ON disable conditions are met, a high level of this signal causes an OFF-to-ACTIVE state transition of the device and a low level causes a transition back to the OFF state.

This input signal is level-sensitive and no debouncing is applied. The rising edge, falling edge, or both of PWRHOLD is highlighted through an associated interrupt if interrupt is unmasked.

When AUTODEV_ON = 1, the pin is used as a GPI. As a GPI, this input can generate a maskable interrupt from a rising or falling edge of the input. When AUTODEV_ON = 1, a rising edge of NRESPWRON also automatically sets the DEV_ON bit to 1 to maintain supplies after the switch-on sequence, thus removing the need for the processor to set the PWRHOLD signal or the DEV_ON bit.

8.4.1.3.3 BOOT1

This signal determines with which processor the device is working and, hence, which power-up sequence is needed. For more details, see . There is no debouncing on this input signal.

8.4.1.3.4 NRESPWRON, NRESPWRON2

The NRESPWRON signal is used as the reset to the processor and is in the VDDIO domain. This signal is held low until the ACTIVE state is reached. For more details, see .

The NRESPWRON2 signal is a second reset output. This signal follows the state of NRESPWRON but has an open-drain output with external pullup. The supply for the external pullup must not be activated before the TPS659119-Q1 device is in control of the output state (that is, not earlier than during first power-up sequence slot). In off mode, the NRESPWRON2 output has a weak internal pulldown.

8.4.1.3.5 CLK32KOUT

This signal is the output of the 32-K oscillator, which can be enabled during the power-on sequence, depending on the boot mode. This signal is enabled and disabled by a register bit during the ACTIVE state of the device. The CLK32KOUT output can also be enabled during the SLEEP state of the device depending on the programming of the SLEEPMASK register.

8.4.1.3.6 PWRON

The PWRON input is connected to an external button. If the device is in the OFF or SLEEP state, a debounced falling edge (PWRON input low for minimum of 100 µs) causes an OFF-to-ACTIVE state or a SLEEP-to-ACTIVE state transition of the device. If the device is in active mode, then a low level on this signal generates an interrupt. If the PWRON signal is low for more than the PWON_TO_OFF_DELAY delay and the corresponding interrupt is not acknowledged by the processor within 1 s, the device enters the OFF state. See Figure 2 and Figure 3 for PWRON behavior.

8.4.1.3.7 INT1

The INT1 signal (default active low) warns the host processor of any event that has occurred on the TPS659119-Q1 device. The host processor can then poll the interrupt from the interrupt status register through I2C to identify the interrupt source. A low level (default setting) indicates an active interrupt, highlighted in the INT_STS_REG register. The polarity of INT1 can be set programming the IT_POL control bit. INT1 flag active is a POWER ON enable condition during a fixed delay, tDOINT1 (only), when the device is in the OFF state (when NRESPWRON is low).

Any of the interrupt sources can be masked programming the INT_MSK_REG register. When an interrupt is masked its corresponding interrupt status bit is still updated, but the INT1 flag is not activated. Interrupt source masking can be used to mask a device switch-on event. Because interrupt flag active is a POWER ON enable condition, during tDOINT1 delay, any interrupt not masked must be cleared to allow immediate turn off of the device.

For a description of interrupt sources, see Table 6.

8.4.1.3.8 EN2 and EN1

EN2 and EN1 are the data and clock signals of the serial-control interface dedicated to voltage-scaling applications.

These signals can also be programmed as enable signals of one or several supplies when the device is on (NRESPWRON high). A resource assigned to EN2 or EN1 control automatically disables the serial control interface.

For the EN1_LDO_ASS_REG, EN2_LDO_REG, and SLEEP_KEEP_LDO_ON_REG registers, the EN1 and EN2 signals can be used to control the ACTIVE or SLEEP state of any LDO-type supplies.

For the EN1_SMPS_ASS_REG, EN2_SMPS_ASS_REG, and SLEEP_KEEP_RES_ON registers, the EN1 and EN2 signals can be used to control the ACTIVE or LOW-POWER state (PFM mode) of SMPS-type supplies.

The EN2 and EN1 signals can set the output voltage of the VDD1 and VDD2 SMPS from a roof to a floor value, preprogrammed in the VDD1_OP_REG, VDD2_OP_REG and VDD1_SR_REG, VDD2_SR_REG registers.

When a supply is controlled through the EN1 or EN2 signals, the state of the supply is no longer driven by the device SLEEP state.

8.4.1.3.9 GPIO0–8

GPIO0, GPIO2, and GPIO6–7 can be programmed as part of the power-up sequence and used as enable signals for external resources.

GPIO0 is a configurable I/O in the VCC7 domain. By default, the output of GPIO0 is push-pull, driving low. GPIO0 can also be configured as an open-drain output with an external pullup.

GPIO1 through GPIO8 are configurable open-drain digital I/Os in the VRTC domain. GPIO directivity, debouncing delay, and internal pullup can be programmed. By default, all are inputs with weak internal pulldown because open-drain output an external pullup is required.

GPIO0–1 and GPIO3–5 can turn on the device if the corresponding interrupt is not masked. When configured as an input, GPIO2 cannot be used to turn on the device, even if the associated interrupt is not masked. The GPIO interrupt is level sensitive. When an interrupt is detected, before clearing the interrupt, it should first be disabled by masking it.

GPIO1 and GPIO3 have a current-sink capability of 10 mA, and can also drive LEDs connected to a 5-V supply.

GPIO2 can be used for synchronizing DCDCs to an external clock. Programming DCDCCKEXT = 1, VDD1, VDD2, and VIO DC-DC switching can be synchronized using a 3-MHz clock set though the GPIO2 pin. VDD1 and VDD2 are in-phase and VIO is phase shifted by 180 degrees.

Not connecting noisy switching signals to GPIO4 and GPIO5 is recommended.

8.4.1.3.10 HDRST Input

HDRST is a cold reset input for the PMIC. A high level at the input forces the TPS659119-Q1 into off mode, causing a general reset of the device to the default settings. The default state is defined by the register reset state and boot configuration. An HDRST high level keeps the device in off mode. When reset is released and HDRST input goes low, the device automatically transitions to active mode. The device is kept in active mode for the period tDONIT1, after which another power-on enable reason is required to keep the device on.

The HDRST input is in the VRTC domain and has a weak internal pulldown which is active by default.

8.4.1.3.11 PWRDN

The PWRDN input is a reset input with selectable polarity (PWRDN_POL). A high level with active-low polarity at the input forces the TPS659119-Q1 device into off mode, causing a power-off reset. Off mode is maintained until PWRDN is released and a start-up reason is detected such as a PWRON button press or DEV_ON = 1. An interrupt is generated to indicate the cause for shutdown. The PWRDN input is in the VRTC domain, but can tolerate a 5-V input.

8.4.1.3.12 Watchdog

The watchdog has two modes of operation.

In periodic operation an interrupt is generated with a regular period defined by the WTCHDG_TIME setting. The IC initiates WTCHDOG shutdown if the interrupt is not cleared within the period. The watchdog interrupt WTCHDOG counter is reinitialized when NRESPWRON is low.

In interrupt mode the IC initiates WTCHDOG counter when an interrupt is pending and is cleared when the interrupt is acknowledged. If the interrupt is not cleared before watchdog expiration within WTCHDG_TIME, the device enters off mode.

By default, periodic watchdog functionality is enabled with the maximum WTCHDG_TIME period.

TPS659119-Q1 SWCS049-013.gif Figure 18. Watchdog Signals

8.4.1.3.13 Tracking LDO

LDO4 has an optional mode where the output level follows that of VDD1, from 0.6 to 1.5 V, when VDD1 is active. When VDD1 is set to off, the LDO4 output is defined by the SEL[7:2] bits in LDO4_REG, and can be set from 0.8 to 1.5 V.

Tracking mode is enabled by setting TRACK = 1 in DCDCCTRL_REG. In initial activation, VDD1 must be enabled and allowed to settle before enabling tracking mode. After initial activation, tracking mode can remain enabled while VDD1 is turned off. The value of TRACK is set to the default (0) after any turnoff event.

TPS659119-Q1 SWCS049-019.gif Figure 19. Tracking LDO

8.5 Programming

8.5.1 Time-Calendar Registers

All time and calendar information is available in these dedicated registers, called TC registers. Values of the TC registers are written in BCD format.

  1. Year data ranges from 00 to 99
    • Leap year = year divisible by four (2000, 2004, 2008, 2012, and so on)
    • Common year = other years
  2. Month data ranges from 1 to 12
  3. Day data ranges from the following:
    • 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12
    • 1 to 30 when months are 4, 6, 9, 11
    • 1 to 29 when month is 2 and year is a leap year
    • 1 to 28 when month is 2 and year is a common year
  4. Week data ranges from 0 to 6
  5. Hour data ranges from 00 to 23 in 24-hour mode and ranges from 1 to 12 in AM/PM mode
  6. Minute data ranges from 0 to 59
  7. Second data ranges from 0 to 59

To modify the current time, software writes the new time into TC registers to fix the time-calendar information. The processor can write to the TC registers without stopping the RTC. In addition, software can stop the RTC by clearing the STOP_RTC bit of the control register, checking the RUN bit of the status to ensure that the RTC is frozen, updating the TC values, and restarting the RTC by setting STOP_RTC bit. An example follows.

Table 5 lists the previous register values for the following example:

Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5

Table 5. Real-Time Clock Registers Example

REGISTER VALUE
SECONDS_REG 0x36
MINUTES_REG 0x54
HOURS_REG 0x90
DAYS_REG 0x05
MONTHS_REG 0x09
YEARS_REG 0x08

The user can round to the closest minute by setting the ROUND_30S register bit. TC values are set to the closest minute value at the next second. The ROUND_30S bit is automatically cleared when the rounding time is performed. Two examples follow:

  • If the current time is 10H59M45S, a round operation changes time to 11H00M00S.
  • if the current time is 10H59M29S, a round operation changes time to 10H59M00S.

8.5.2 General Registers

Software can access the RTC_STATUS_REG and RTC_CTRL_REG registers at any time. The only exception is that software cannot access the RTC_CTRL_REG[5] bit which must be changed only when the RTC is stopped.

8.5.3 Compensation Registers

The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers must be updated before each compensation process. For example, software can load the compensation value into these registers after each hour event during an available access period.

TPS659119-Q1 SWCS049-016.gif Figure 20. RTC Compensation Scheduling

This drift can be balanced to compensate for any inaccuracy of the 32-kHz oscillator. Software must calibrate the oscillator frequency, calculate the drift compensation versus 1-h time period, and load the compensation registers with the drift compensation value. If the AUTO_COMP_EN bit in the RTC_CTRL_REG is enabled, the value of COMP_REG (in twos-complement) is added to the RTC 32-kHz counter at the first second of each hour. When COMP_REG is added to the RTC 32-kHz counter, the duration of the current second becomes (32768 – COMP_REG) / 32768 s; so, the RTC can be compensated with a 1 / 32768 s/hour time unit accuracy.

NOTE

The compensation is considered when written into the registers.

8.5.4 Backup Registers

As part of the RTC, the device contains five 8-bit registers that can be used for storage by the application firmware when the external host is powered down. These registers retain the content as long as the VRTC is active.

8.5.5 I2C Interface

A general-purpose serial-control interface (CTL-I2C) allows read and write access to the configuration registers of all resources of the system.

A second serial-control interface (optional mode for EN1 and EN2 pins) can be dedicated to DVFS.

Both control interfaces are compliant with the HS-I2C specification.

These interfaces support the standard slave mode (100 Kbps), fast mode (400 Kbps), and high-speed mode (3.4 Mbps). The general-purpose I2C module using one slave hard-coded address (ID1 = 2Dh). The voltage scaling dedicated I2C module uses one slave hardcoded address (ID0 = 12h). The master mode is not supported.

8.5.5.1 Addressing

The device supports seven-bit mode addressing.

It does not support the following features:

  • 10-bit addressing
  • General call

8.5.5.2 Access Protocols

Access protocols or compatibility, the I2C interfaces in the TPS659119-Q1 device use the same read and write protocol as other TI power ICs, based on an internal register size of 8 bits. Supported transactions are described below.

8.5.5.2.1 Single-Byte Access

A write access is initiated by a first byte including the address of the device (7 MSBs) and a write command (LSB), a second byte provides the address (8 bits) of the internal register, and the third byte represents the data to be written in the internal register (see Figure 21).

A read access is initiated by:

  • A first byte, including the address of the device (7 MSBs) and a write command (LSB)
  • A second byte, providing the address (8 bits) of the internal register
  • A third byte, including again the device address (7 MSBs) and the read command (LSB)

The device replies by sending a fourth byte which represents the content of the internal register (see Figure 22).

TPS659119-Q1 SWCS049-020.gif Figure 21. I2C Write-Access Single Byte
TPS659119-Q1 SWCS049-021.gif Figure 22. I2C Read-Access Single Byte

8.5.5.2.2 Multiple-Byte Access To Several Adjacent Registers

A write access is initiated by:

  • A first byte, including the address of the device (7 MSBs) and a write command (LSB)
  • A second byte, providing the base address (8 bits) of the internal registers

The following N bytes represent the data to be written in the internal register starting at the base address and incremented by one at each data byte (see Figure 23).

A read access is initiated by:

  • A first byte, including the address of the device (7 MSBs) and a write command (LSB)
  • A second byte, providing the base address (8 bits) of the internal register
  • A third byte, including again the device address (7 MSBs) and the read command (LSB)

The device replies by sending a fourth byte, which represents the content of the internal registers, starting at the base address and next consecutive ones (see Figure 24).

TPS659119-Q1 SWCS049-022.gif Figure 23. I2C Write-Access Multiple Bytes
TPS659119-Q1 SWCS049-023.gif Figure 24. I2C Read-Access Multiple Bytes

8.5.6 Interrupts

Table 6. Interrupt Sources

INTERRUPT DESCRIPTION
RTC_ALARM_IT RTC alarm event: Occurs at programmed determinate date and time
(running in ACTIVE, OFF, and SLEEP state, default inactive)
RTC_PERIOD_IT RTC periodic event: Occurs at programmed regular period of time (every second or minute) (running in ACTIVE, OFF, and SLEEP state, default inactive)
HOT_DIE_IT The embedded thermal monitoring module detects a die temperature above the hot-die detection threshold (running in ACTIVE and SLEEP state).
Level sensitive interrupt.
PWRHOLD_R_IT PWRHOLD signal rising edge
PWRHOLD_F_IT PWRHOLD signal falling-edge
PWRON_LP_IT PWRON is low during more than the long-press delay: PWON_TO_OFF_DELAY (can be disable though register programming).
PWRON_IT PWRON is low while the device is on (running in ACTIVE and SLEEP state). Level-sensitive interrupt.
GPIO0_R_IT GPIO_CKSYNC rising-edge detection
GPIO0_F_IT GPIO_CKSYNC falling-edge detection
GPIO1_R_IT GPIO1 rising-edge detection
GPIO1_F_IT GPIO1 falling-edge detection
GPIO2_R_IT GPIO2 rising-edge detection
GPIO2_F_IT GPIO2 falling-edge detection
GPIO3_R_IT GPIO3 rising-edge detection
GPIO3_F_IT GPIO3 falling-edge detection
GPIO4_R_IT GPIO4 rising-edge detection
GPIO4_F_IT GPIO4 falling-edge detection
GPIO5_R_IT GPIO5 rising-edge detection
GPIO5_F_IT GPIO5 falling-edge detection
WTCHDG_IT Watchdog interrupt
PWRDN_IT PWRDN reset interrupt

8.6 Register Maps

8.6.1 Functional Registers

The possible device reset domains are:

  • Full reset: All digital of device is reset.
    • Caused by Power On Reset (POR) when VCCS < VBNPR
  • General reset: No impact on RTC, backup registers or interrupt status.
    • Caused by PWON_LP_RST bit set high or
    • DEV_OFF_RST bit set high or
    • HDRST input set high
  • Turnoff OFF: Power reinitialization in off or backup mode.

In following register description, reset domain for each register is defined at the register table heading.

NOTE

The DCDCCTRL_REG and DEVCTRL2_REG have bits in two reset domains.

The comment, Default value: See boot configuration, indicates that the default value of the bit is set in boot configuration and not by register reset value.

8.6.2 TPS659119-Q1_FUNC_REG Register Mapping Summary

Table 7. TPS659119-Q1_FUNC_REG Register Summary(1)

REGISTER NAME TYPE REGISTER WIDTH (BITS) REGISTER RESET ADDRESS OFFSET
SECONDS_REG RW 8 0x00 0x00
MINUTES_REG RW 8 0x00 0x01
HOURS_REG RW 8 0x00 0x02
DAYS_REG RW 8 0x01 0x03
MONTHS_REG RW 8 0x01 0x04
YEARS_REG RW 8 0x00 0x05
WEEKS_REG RW 8 0x00 0x06
ALARM_SECONDS_REG RW 8 0x00 0x08
ALARM_MINUTES_REG RW 8 0x00 0x09
ALARM_HOURS_REG RW 8 0x00 0x0A
ALARM_DAYS_REG RW 8 0x01 0x0B
ALARM_MONTHS_REG RW 8 0x01 0x0C
ALARM_YEARS_REG RW 8 0x00 0x0D
RTC_CTRL_REG RW 8 0x00 0x10
RTC_STATUS_REG RW 8 0x80 0x11
RTC_INTERRUPTS_REG RW 8 0x00 0x12
RTC_COMP_LSB_REG RW 8 0x00 0x13
RTC_COMP_MSB_REG RW 8 0x00 0x14
RTC_RES_PROG_REG RW 8 0x27 0x15
RTC_RESET_STATUS_REG RW 8 0x00 0x16
BCK1_REG RW 8 0x00 0x17
BCK2_REG RW 8 0x00 0x18
BCK3_REG RW 8 0x00 0x19
BCK4_REG RW 8 0x00 0x1A
BCK5_REG RW 8 0x00 0x1B
PUADEN_REG RW 8 0x1F 0x1C
REF_REG RO 8 0x01 0x1D
VRTC_REG RW 8 0x01 0x1E
VIO_REG RW 8 0x05 0x20
VDD1_REG RW 8 0x0D 0x21
VDD1_OP_REG RW 8 0x33 0x22
VDD1_SR_REG RW 8 0x33 0x23
VDD2_REG RW 8 0x0D 0x24
VDD2_OP_REG RW 8 0x4B 0x25
VDD2_SR_REG RW 8 0x4B 0x26
EXTCTRL_REG RW 8 0x00 0x27
EXTCTRL_OP_REG RW 8 0x03 0x28
EXTCTRL_SR_REG RW 8 0x03 0x29
LDO1_REG RW 8 0x15 0x30
LDO2_REG RW 8 0x15 0x31
LDO5_REG RW 8 0x00 0x32
LDO8_REG RW 8 0x09 0x33
LDO7_REG RW 8 0x0D 0x34
LDO6_REG RW 8 0x21 0x35
LDO4_REG RW 8 0x00 0x36
LD03_REG RW 8 0x00 0x37
THERM_REG RW 8 0x0D 0x38
BBCH_REG RW 8 0x00 0x39
DCDCCTRL_REG RW 8 0x39 0x3E
DEVCTRL_REG RW 8 0x0000 0014 0x3F
DEVCTRL2_REG RW 8 0x0000 0036 0x40
SLEEP_KEEP_LDO_ON_REG RW 8 0x00 0x41
SLEEP_KEEP_RES_ON_REG RW 8 0x00 0x42
SLEEP_SET_LDO_OFF_REG RW 8 0x00 0x43
SLEEP_SET_RES_OFF_REG RW 8 0x00 0x44
EN1_LDO_ASS_REG RW 8 0x00 0x45
EN1_SMPS_ASS_REG RW 8 0x00 0x46
EN2_LDO_ASS_REG RW 8 0x00 0x47
EN2_SMPS_ASS_REG RW 8 0x00 0x48
INT_STS_REG RW 8 0x06 0x50
INT_MSK_REG RW 8 0xFF 0x51
INT_STS2_REG RW 8 0xA8 0x52
INT_MSK2_REG RW 8 0xFF 0x53
INT_STS3_REG RW 8 0x5A 0x54
INT_MSK3_REG RW 8 0xFF 0x55
GPIO0_REG RW 8 0x07 0x60
GPIO1_REG RW 8 0x08 0x61
GPIO2_REG RW 8 0x08 0x62
GPIO3_REG RW 8 0x08 0x63
GPIO4_REG RW 8 0x08 0x64
GPIO5_REG RW 8 0x08 0x65
GPIO6_REG RW 8 0x05 0x66
GPIO7_REG RW 8 0x05 0x67
GPIO8_REG RW 8 0x08 0x68
WATCHDOG_REG RW 8 0x07 0x69
BOOTSEQVER_REG RW 8 0x1E 0x6A
VMBCH2_REG RW 8 0x00 0x6B
LED_CTRL1_REG RW 8 0x00 0x6C
LED_CTRL2_REG1 RW 8 0x00 0x6D
PWM_CTRL1_REG RW 8 0x00 0x6E
PWM_CTRL2_REG RW 8 0x00 0x6F
SPARE_REG RW 8 0x00 0x70
VERNUM_REG RO 8 0x00 0x80
(1) Register reset values are for fixed boot mode.

8.6.3 TPS659119-Q1_FUNC_REG Register Descriptions

Table 8. SECONDS_REG

Address Offset 0x00
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register for seconds
Type RW

7 6 5 4 3 2 1 0
Reserved SEC1 SEC0

BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved Reserved bit RO
R returns 0s 		0
6:4 SEC1 Second digit of seconds (range is 0 up to 5) RW 0x0
3:0 SEC0 First digit of seconds (range is 0 up to 9) RW 0x0

Table 9. MINUTES_REG

Address Offset 0x01
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register for minutes
Type RW

7 6 5 4 3 2 1 0
Reserved MIN1 MIN0

BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved Reserved bit RO
R returns 0s 		0
6:4 MIN1 Second digit of minutes (range is 0 up to 5) RW 0x0
3:0 MIN0 First digit of minutes (range is 0 up to 9) RW 0x0

Table 10. HOURS_REG

Address Offset 0x02
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register for hours
Type RW

7 6 5 4 3 2 1 0
PM_NAM Reserved HOUR1 HOUR0

BITS FIELD NAME DESCRIPTION TYPE RESET
7 PM_NAM Only used in PM_AM mode (otherwise it is set to 0)
0 is AM
1 is PM 		RW 0
6 Reserved Reserved bit RO
R returns 0s 		0
5:4 HOUR1 Second digit of hours(range is 0 up to 2) RW 0x0
3:0 HOUR0 First digit of hours (range is 0 up to 9) RW 0x0

Table 11. DAYS_REG

Address Offset 0x03
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register for days
Type RW

7 6 5 4 3 2 1 0
Reserved DAY1 DAY0

BITS FIELD NAME DESCRIPTION TYPE RESET
7:6 Reserved Reserved bit RO
R returns 0s 		0x0
5:4 DAY1 Second digit of days (range is 0 up to 3) RW 0x0
3:0 DAY0 First digit of days (range is 0 up to 9) RW 0x1

Table 12. MONTHS_REG

Address Offset 0x04
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register for months
Type RW

7 6 5 4 3 2 1 0
Reserved MONTH1 MONTH0

BITS FIELD NAME DESCRIPTION TYPE RESET
7:5 Reserved Reserved bit RO
R returns 0s 		0x0
4 MONTH1 Second digit of months (range is 0 up to 1) RW 0
3:0 MONTH0 First digit of months (range is 0 up to 9) RW 0x1

Table 13. YEARS_REG

Address Offset 0x05
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register for day of the week
Type RW

7 6 5 4 3 2 1 0
YEAR1 YEAR0

BITS FIELD NAME DESCRIPTION TYPE RESET
7:4 YEAR1 Second digit of years (range is 0 up to 9) RW 0x0
3:0 YEAR0 First digit of years (range is 0 up to 9) RW 0x0

Table 14. WEEKS_REG

Address Offset 0x06
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register for day of the week
Type RW

7 6 5 4 3 2 1 0
Reserved WEEK

BITS FIELD NAME DESCRIPTION TYPE RESET
7:3 Reserved Reserved bit RO
R returns 0s 		0x00
2:0 WEEK First digit of day of the week (range is 0 up to 6) RW 0

Table 15. ALARM_SECONDS_REG

Address Offset 0x08
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register for programming seconds in the alarm setting
Type RW

7 6 5 4 3 2 1 0
Reserved ALARM_SEC1 ALARM_SEC0

BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved Reserved bit RO
R returns 0s 		0
6:4 ALARM_SEC1 Second digit for programming seconds in the alarm setting (range is 0 up to 5) RW 0x0
3:0 ALARM_SEC0 First digit for programming seconds in the alarm setting (range is 0 up to 9) RW 0x0

Table 16. ALARM_MINUTES_REG

Address Offset 0x09
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register for programming minutes in the alarm setting
Type RW

7 6 5 4 3 2 1 0
Reserved ALARM_MIN1 ALARM_MIN0

BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved Reserved bit RO
R returns 0s 		0
6:4 ALARM_MIN1 Second digit for programming minutes in the alarm setting (range is 0 up to 5) RW 0x0
3:0 ALARM_MIN0 First digit for programming minutes in the alarm setting (range is 0 up to 9) RW 0x0

Table 17. ALARM_HOURS_REG

Address Offset 0x0A
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register for programming hours in the alarm setting
Type RW

7 6 5 4 3 2 1 0
ALARM_PM_NAM Reserved ALARM_HOUR1 ALARM_HOUR0

BITS FIELD NAME DESCRIPTION TYPE RESET
7 ALARM_PM_NAM Only used in PM_AM mode for programming the AM/PM in the alarm setting (otherwise it is set to 0)
0 is AM
1 is PM 		RW 0
6 Reserved Reserved bit RO
R returns 0s		 0
5:4 ALARM_HOUR1 Second digit for programming hours in the alarm setting (range is 0 up to 2) RW 0x0
3:0 ALARM_HOUR0 First digit for programming hours in the alarm setting (range is 0 up to 9) RW 0x0

Table 18. ALARM_DAYS_REG

Address Offset 0x0B
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register for programming days in the alarm setting
Type RW

7 6 5 4 3 2 1 0
Reserved ALARM_DAY1 ALARM_DAY0

BITS FIELD NAME DESCRIPTION TYPE RESET
7:6 Reserved Reserved bit RO
R Special		 0x0
5:4 ALARM_DAY1 Second digit for programming days in the alarm setting (range is 0 up to 3) RW 0x0
3:0 ALARM_DAY0 First digit for programming days in the alarm setting (range is 0 up to 9) RW 0x1

Table 19. ALARM_MONTHS_REG

Address Offset 0x0C
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register for programming months in the alarm setting
Type RW

7 6 5 4 3 2 1 0
Reserved ALARM_MONTH1 ALARM_MONTH0

BITS FIELD NAME DESCRIPTION TYPE RESET
7:5 Reserved Reserved bit RO
R returns 0s 		0x0
4 ALARM_MONTH1 Second digit for programming months in the alarm setting(range is 0 up to 1) RW 0
3:0 ALARM_MONTH0 First digit for programming months in the alarm setting(range is 0 up to 9) RW 0x1

Table 20. ALARM_YEARS_REG

Address Offset 0x0D
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register for programming years in the alarm setting
Type RW

7 6 5 4 3 2 1 0
ALARM_YEAR1 ALARM_YEAR0

BITS FIELD NAME DESCRIPTION TYPE RESET
7:4 ALARM_YEAR1 Second digit for programming years in the alarm setting (range is 0 up to 9) RW 0x0
3:0 ALARM_YEAR0 First digit for programming years in the alarm setting (range is 0 up to 9) RW 0x0

Table 21. RTC_CTRL_REG

Address Offset 0x10
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC control register:
Note: A dummy read of this register is necessary before each I2C read in order to update the ROUND_30S bit value.
Type RW

7 6 5 4 3 2 1 0
RTC_V_OPT GET_TIME SET_32_COUNTER TEST_MODE MODE_12_24 AUTO_COMP ROUND_30S STOP_RTC

BITS FIELD NAME DESCRIPTION TYPE RESET
7 RTC_V_OPT RTC date and time register selection:
0: Read access directly to dynamic registers (SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, MONTHS_REG, YEAR_REG, WEEKS_REG)
1: Read access to static shadowed registers: (see GET_TIME bit). 		RW 0
6 GET_TIME When writing a 1 into this register, the content of the dynamic registers (SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, MONTHS_REG, YEAR_REG and WEEKS_REG) is transferred into static shadowed registers. Each update of the shadowed registers needs to be done by re-asserting GET_TIME bit to 1 (In effect: reset it to 0 and then re-write it to 1) RW 0
5 SET_32_COUNTER 0: No action
1: set the 32-kHz counter with COMP_REG value.
It must only be used when the RTC is frozen. 		RW 0
4 TEST_MODE 0: functional mode
1: test mode (Auto compensation is enable when the 32-kHz counter reaches at the end of the counter) 		RW 0
3 MODE_12_24 0: 24-hours mode
1: 12-hours mode (PM-AM mode)
Switching between the two modes at any time without disturbing the RTC is possible. Read or write are always performed with the current mode. 		RW 0
2 AUTO_COMP 0: No auto compensation
1: Auto compensation enabled 		RW 0
1 ROUND_30S 0: No update
1: When a one is written, the time is rounded to the closest minute.
This bit is a toggle bit, the micro-controller can only write one and RTC clears it. If the micro-controller sets the ROUND_30S bit and then read it, the micro-controller reads one until the rounded to the closet.		 RW 0
0 STOP_RTC 0: RTC is frozen
1: RTC is running 		RW 0

Table 22. RTC_STATUS_REG

Address Offset 0x11
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC status register:
Note: A dummy read of this register is necessary before each I2C read in order to update the status register value.
Type RW

7 6 5 4 3 2 1 0
POWER_UP ALARM EVENT_1D EVENT_1H EVENT_1M EVENT_1S RUN Reserved

BITS FIELD NAME DESCRIPTION TYPE RESET
7 POWER_UP Indicates that a reset occurred (bit cleared to 0 by writing 1).
POWER_UP is set by a reset, is cleared by writing one in this bit. 		RW 1
6 ALARM Indicates that an alarm interrupt is generated (bit clear by writing 1).
The alarm interrupt keeps its low level, until the micro-controller write 1 in the ALARM bit of the RTC_STATUS_REG register.
The timer interrupt is a low-level pulse (15 µs duration). 		RW 0
5 EVENT_1D One day has occurred RO 0
4 EVENT_1H One hour has occurred RO 0
3 EVENT_1M One minute has occurred RO 0
2 EVENT_1S One second has occurred RO 0
1 RUN 0: RTC is frozen
1: RTC is running
This bit shows the real state of the RTC, because STOP_RTC signal was resynchronized on 32-kHz clock, the action of this bit is delayed. 		RO 0
0 Reserved Reserved bit RO
R returns 0s 		0

Table 23. RTC_INTERRUPTS_REG

Address Offset 0x12
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC interrupt-control register
Type RW

7 6 5 4 3 2 1 0
Reserved IT_SLEEP_MASK_EN IT_ALARM IT_TIMER EVERY

BITS FIELD NAME DESCRIPTION TYPE RESET
7:5 Reserved Reserved bit RO
R returns 0s 		0x0
4 IT_SLEEP_MASK_EN 1: Mask periodic interrupt while the TPS659119-Q1 device is in SLEEP mode. The interrupt event is back up in a register and occurs as soon as the TPS659119-Q1 device is no longer in SLEEP mode.
0: Normal mode, no interrupt masked 		RW 0
3 IT_ALARM Enable one interrupt when the alarm value is reached (TC ALARM registers) by the TC registers RW 0
2 IT_TIMER Enable periodic interrupt
0: interrupt disabled
1: interrupt enabled 		RW 0
1:0 EVERY Interrupt period
00: every second
01: every minute
10: every hour
11: every day 		RW 0x0

Table 24. RTC_COMP_LSB_REG

Address Offset 0x13
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC compensation register (LSB)
Note: This register must be written in twos-complement.
Which means that to add one 32-kHz oscillator period every hour, the microcontroller muse write FFFF into RTC_COMP_MSB_REG & RTC_COMP_LSB_REG.
To remove one 32-kHz oscillator period every hour, the microcontroller needs to write 0001 into RTC_COMP_MSB_REG & RTC_COMP_LSB_REG.
The 7FFF value is forbidden.
Type RW

7 6 5 4 3 2 1 0
RTC_COMP_LSB

BITS FIELD NAME DESCRIPTION TYPE RESET
7:0 RTC_COMP_LSB This register contains the number of 32-kHz periods to be added into the 32-kHz counter every hour [LSB] RW 0x00

Table 25. RTC_COMP_MSB_REG

Address Offset 0x14
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC compensation register (MSB)
Notes: See RTC_COMP_LSB_REG Notes.
Type RW

7 6 5 4 3 2 1 0
RTC_COMP_MSB

BITS FIELD NAME DESCRIPTION TYPE RESET
7:0 RTC_COMP_MSB This register contains the number of 32-kHz periods to be added into the 32-kHz counter every hour [MSB] RW 0x00

Table 26. RTC_RES_PROG_REG

Address Offset 0x15
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register containing oscillator resistance value
Type RW

7 6 5 4 3 2 1 0
Reserved SW_RES_PROG

BITS FIELD NAME DESCRIPTION TYPE RESET
7:6 Reserved Reserved bit RO
R returns 0s 		0x0
5:0 SW_RES_PROG Value of the oscillator resistance RW 0x27

Table 27. RTC_RESET_STATUS_REG

Address Offset 0x16
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register for reset status
Type RW

7 6 5 4 3 2 1 0
Reserved RESET_STATUS

BITS FIELD NAME DESCRIPTION TYPE RESET
7:1 Reserved Reserved bit RO
R returns 0s 		0x0
0 RESET_STATUS This bit can only be set to one and is cleared when a manual reset or a POR (VBAT < 2.1) occur. If this bit is reset the RTC lost its configuration. RW 0

Table 28. BCK1_REG

Address Offset 0x17
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description Backup register which can be used for storage by the application firmware when the external host is powered down. These registers retain content as long as the VRTC is active.
Type RW

7 6 5 4 3 2 1 0
BCKUP

BITS FIELD NAME DESCRIPTION TYPE RESET
7:0 BCKUP Backup bit RW 0x00

Table 29. BCK2_REG

Address Offset 0x18
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description Backup register which can be used for storage by the application firmware when the external host is powered down. These registers retain content as long as the VRTC is active.
Type RW

7 6 5 4 3 2 1 0
BCKUP

BITS FIELD NAME DESCRIPTION TYPE RESET
7:0 BCKUP Backup bit RW 0x00

Table 30. BCK3_REG

Address Offset 0x19
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description Backup register which can be used for storage by the application firmware when the external host is powered down. These registers retain content as long as the VRTC is active.
Type RW

7 6 5 4 3 2 1 0
BCKUP

BITS FIELD NAME DESCRIPTION TYPE RESET
7:0 BCKUP Backup bit RW 0x00

Table 31. BCK4_REG

Address Offset 0x1A
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description Backup register which can be used for storage by the application firmware when the external host is powered down. These registers retain content as long as the VRTC is active.
Type RW

7 6 5 4 3 2 1 0
BCKUP

BITS FIELD NAME DESCRIPTION TYPE RESET
7:0 BCKUP Backup bit RW 0x00

Table 32. BCK5_REG

Address Offset 0x1B
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description Backup register which can be used for storage by the application firmware when the external host is powered down. These registers retain content as long as the VRTC is active.
Type RW

7 6 5 4 3 2 1 0
BCKUP

BITS FIELD NAME DESCRIPTION TYPE RESET
7:0 BCKUP Backup bit RW 0x00

Table 33. PUADEN_REG

Address Offset 0x1C
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description Pullup and pulldown control register.
Type RW

7 6 5 4 3 2 1 0
Reserved I2CCTLP I2CSRP PWRONP SLEEPP PWRHOLDP HDRSTP NRESPWRON2P

BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved RO 0
6 I2CCTLP SDACTL and SCLCTL pullup control:
1: Pullup is enabled
0: Pullup is disabled 		RW 0
5 I2CSRP SDASR and SCLSR pullup control:
1: Pullup is enabled
0: Pullup is disabled 		RW 0
4 PWRONP PWRON-pad pullup control:
1: Pullup is enabled
0: Pullup is disabled 		RW 1
3 SLEEPP SLEEP-pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1
2 PWRHOLDP PWRHOLD-pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1
1 HDRSTP HDRST-pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1
0 NRESPWRON2P NRESPWRON2 pad control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1

Table 34. REF_REG

Address Offset 0x1D
Physical Address Instance (RESET DOMAIN: TURNOFF OFF RESET)
Description Reference control register
Type RO

7 6 5 4 3 2 1 0
Reserved ST

BITS FIELD NAME DESCRIPTION TYPE RESET
7:2 Reserved Reserved bit RO
R returns 0s 		0x00
1:0 ST Reference state:
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Reserved
ST[1:0] = 11: On low power (SLEEP)
(Write access available in test mode only) 		RO 0x1

Table 35. VRTC_REG

Address Offset 0x1E
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description VRTC internal regulator control register
Type RW

7 6 5 4 3 2 1 0
Reserved VRTC_OFFMASK Reserved ST

BITS FIELD NAME DESCRIPTION TYPE RESET
7:4 Reserved Reserved bit RO
R returns 0s 		0x0
3 VRTC_OFFMASK VRTC internal regulator off mask signal:
When set to 1, the regulator keeps its full-load capability during device OFF state.
When set to 0, the regulator enters in low-power mode during device OFF state.
Note that VRTC enters low-power mode when the device is on backup even if this bit is set to 1 (Default value: See boot configuration) 		RW 0
2 Reserved Reserved bit RO
R returns 0s 		0
1:0 ST Reference state:
ST[1:0] = 00: Reserved
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Reserved
ST[1:0] = 11: On low power (SLEEP)
(Write access available in test mode only) 		RO 0x1

Table 36. VIO_REG

Address Offset 0x20
Physical Address Instance (RESET DOMAIN: TURNOFF OFF RESET)
Description VIO control register
Type RW

7 6 5 4 3 2 1 0
ILIM Reserved SEL ST

BITS FIELD NAME DESCRIPTION TYPE RESET
7:6 TPS659119xAIPFPRQ1 ILIM Current-limit threshold selection:
ILIM[1:0] = 00: 0.7 A
ILIM[1:0] = 01: 1.2 A
ILIM[1:0] = 10: 1.7 A
ILIM[1:0] = 11: > 1.7 A 		RW 0x0
5:4 Reserved Reserved bit RO
R returns 0s 		0x0
3:2 SEL Output voltage selection (EEPROM bits):
SEL[1:0] = 00: 1.5 V
SEL[1:0] = 01: 1.8 V
SEL[1:0] = 10: 2.5 V
SEL[1:0] = 11: 3.3 V
(Default value: see boot configuration)		 RW 0x0
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: OFF
ST[1:0] = 01: ON high power (ACTIVE)
ST[1:0] = 10: OFF
ST[1:0] = 11: ON low power (SLEEP) 		RW 0x0

Table 37. VDD1_REG

Address Offset 0x21
Physical Address Instance (RESET DOMAIN: TURNOFF OFF RESET)
Description VDD1 control register
Type RW

7 6 5 4 3 2 1 0
VGAIN_SEL ILMAX TSTEP ST

BITS FIELD NAME DESCRIPTION TYPE RESET
7:6 VGAIN_SEL Select output voltage multiplication factor: G (EEPROM bits):
When set to 00: x1
When set to 01: TBD
When set to 10: x2
When set to 11: x3
(Default value: see boot configuration)		 RW 0x0
5:4 ILMAX Select current limit threshold:
When set to 0: 1.2 A
When set to 1: > 1.7 A 		RW 0
3:2 TSTEP Time step: when changing the output voltage, the new value is reached through successive 12.5-mV voltage steps (if not bypassed). The equivalent programmable slew rate of the output voltage is then:
TSTEP[2:0] = 000: step duration is 0, step function is bypassed
TSTEP[2:0] = 001: 12.5 mV/µs (sampling 3 MHz)
TSTEP[2:0] = 010: 9.4 mV/µs (sampling 3 MHz × 3/4)
TSTEP[2:0] = 011: 7.5 mV/µs (sampling 3 MHz × 3/5) (default)
TSTEP[2:0] = 100: 6.25 mV/µs(sampling 3 MHz/2)
TSTEP[2:0] = 101: 4.7 mV/µs(sampling 3 MHz/3)
TSTEP[2:0] = 110: 3.12 mV/µs(sampling 3 MHz/4)
TSTEP[2:0] = 111: 2.5 mV/µs(sampling 3 MHz/5) 		RW 0x3
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: OFF
ST[1:0] = 01: ON, high-power mode
ST[1:0] = 10: OFF
ST[1:0] = 11: ON, low-power mode 		RW 0x0

Table 38. VDD1_OP_REG

Address Offset 0x22
Physical Address Instance (RESET DOMAIN: TURNOFF OFF RESET)
Description VDD1 voltage selection register.
This register can be accessed by both control and voltage-scaling I2C interfaces depending on the SR_CTL_I2C_SEL register bit value.
Type RW

7 6 5 4 3 2 1 0
CMD SEL

BITS FIELD NAME DESCRIPTION TYPE RESET
7 CMD When set to 0: VDD1_OP_REG voltage is applied
When set to 1: VDD1_SR_REG voltage is applied 		RW 0
6:0 SEL Output voltage (4 EEPROM bits) selection with GAIN_SEL = 00 (G = 1, 12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111: 1.5 V
...
SEL[6:0] = 0111111: 1.35 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0000001 to 0000011: 0.6 V
SEL[6:0] = 0000000: Off (0.0 V)
Note: from SEL[6:0] = 3 to 75 (dec)
VOUT = (SEL[6:0] × 12.5 mV + 0.5625 V) × G
(Default value: See boot configuration)		 RW 0x00

Table 39. VDD1_SR_REG

Address Offset 0x23
Physical Address Instance (RESET DOMAIN: TURNOFF OFF RESET)
Description VDD1 voltage selection register.
This register can be accessed by both control and voltage scaling dedicated I2C interfaces depending on SR_CTL_I2C_SEL register bit value.
Type RW

7 6 5 4 3 2 1 0
Reserved SEL

BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved Reserved bit RO
R returns 0s 		0
6:0 SEL Output voltage selection with GAIN_SEL = 00 (G = 1, 12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111: 1.5 V
...
SEL[6:0] = 0111111: 1.35 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0000001 to 0000011: 0.6 V
SEL[6:0] = 0000000: Off (0.0 V)
Note: from SEL[6:0] = 3 to 75 (dec)
VOUT = (SEL[6:0] × 12.5 mV + 0.5625 V) × G
(Default value: See boot configuration)		 RW 0x00

Table 40. VDD2_REG

Address Offset 0x24
Physical Address Instance (RESET DOMAIN: TURNOFF OFF RESET)
Description VDD2 control register
Type RW

7 6 5 4 3 2 1 0
VGAIN_SEL ILMAX TSTEP ST

BITS FIELD NAME DESCRIPTION TYPE RESET
7:6 VGAIN_SEL Select output voltage multiplication factor (x1, x3 included in EEPROM bits): G
When set to 00: x1
When set to 01: TBD
When set to 10: x2
When set to 11: x3 		RW 0x0
5:4 ILMAX Select current limit threshold
When set to 0: 1.2 A
When set to 1: > 1.7 A 		RW 0
3:2 TSTEP Time step: when changing the output voltage, the new value is reached through successive 12.5-mV voltage steps (if not bypassed). The equivalent programmable slew rate of the output voltage is then:
TSTEP[2:0] = 000: step duration is 0, step function is bypassed
TSTEP[2:0] = 001: 12.5 mV/µs (sampling 3 MHz)
TSTEP[2:0] = 010: 9.4 mV/µs (sampling 3 MHz × 3/4)
TSTEP[2:0] = 011: 7.5 mV/µs (sampling 3 MHz × 3/5) (default)
TSTEP[2:0] = 100: 6.25 mV/µs(sampling 3 MHz/2)
TSTEP[2:0] = 101: 4.7 mV/µs(sampling 3 MHz/3)
TSTEP[2:0] = 110: 3.12 mV/µs(sampling 3 MHz/4)
TSTEP[2:0] = 111: 2.5 mV/µs(sampling 3 MHz/5) 		RW 0x1
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: OFF
ST[1:0] = 01: ON, high-power mode
ST[1:0] = 10: OFF
ST[1:0] = 11: ON, low-power mode 		RW 0x0

Table 41. VDD2_OP_REG

Address Offset 0x25
Physical Address Instance (RESET DOMAIN: TURNOFF OFF RESET)
Description VDD2 voltage selection register.
This register can be accessed by both control-dedicated and voltage-scaling-dedicated I2C interfaces depending on the SR_CTL_I2C_SEL register bit value.
Type RW

7 6 5 4 3 2 1 0
CMD SEL

BITS FIELD NAME DESCRIPTION TYPE RESET
7 CMD Command:
When set to 0: VDD2_OP_REG voltage is applied
When set to 1: VDD2_SR_REG voltage is applied 		RW 0
6:0 SEL Output voltage (4 EEPROM bits) selection with GAIN_SEL = 00 (G = 1, 12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111: 1.5 V
...
SEL[6:0] = 0111111: 1.35 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0000001 to 0000011: 0.6 V
SEL[6:0] = 0000000: Off (0.0 V)
Note: from SEL[6:0] = 3 to 75 (dec)
VOUT = (SEL[6:0] × 12.5 mV + 0.5625 V) × G 		RW 0x00

Table 42. VDD2_SR_REG

Address Offset 0x26
Physical Address Instance (RESET DOMAIN: TURNOFF OFF RESET)
Description VDD2 voltage selection register.
This register can be accessed by both control-dedicated and voltage-scaling-dedicated I2C interfaces depending on the SR_CTL_I2C_SEL register bit value.
Type RW

7 6 5 4 3 2 1 0
Reserved SEL

BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved Reserved bit RO
R returns 0s 		0
6:0 SEL Output voltage (EEPROM bits) selection with GAIN_SEL = 00 (G = 1, 12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111: 1.5 V
...
SEL[6:0] = 0111111: 1.35 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0000001 to 0000011: 0.6 V
SEL[6:0] = 0000000: Off (0 V)
Note: from SEL[6:0] = 3 to 75 (dec)
VOUT= (SEL[6:0] × 12.5 mV + 0.5625 V) × G 		RW 0x00

Table 43. EXTCTRL_REG

Address Offset 0x27
Physical Address Instance (RESET DOMAIN: TURNOFF OFF RESET)
Description EXTCTRL, external converter voltage controller
Type RW

7 6 5 4 3 2 1 0
Reserved ST

BITS FIELD NAME DESCRIPTION TYPE RESET
7:2 Reserved Reserved bit RO
R returns 0s 		0x00
1:0 ST Supply state (EEPROM dependent):
ST[1:0] = 00: Off
ST[1:0] = 01: On
ST[1:0] = 10: Off
ST[1:0] = 11: On 		RW 0x0

Table 44. EXTCTRL_OP_REG

Address Offset 0x28
Physical Address Instance (RESET DOMAIN: TURN OFF RESET)
Description EXTCTRL voltage-selection register.
This register can be accessed by both control-dedicated and voltage-scaling-dedicated I2C interfaces depending on the SR_CTL_I2C_SEL register bit value.
Type RW

7 6 5 4 3 2 1 0
CMD SEL

BITS FIELD NAME DESCRIPTION TYPE RESET
7 CMD Command:
When set to 0: EXTCTRL_OP_REG voltage is applied
When set to 1: EXTCTRL_SR_REG voltage is applied		 RW 0
6:0 SEL Resistive divider ratio selection (4 EEPROM bits):
For SEL[6:0] = 3 to 67,
Ratio = 48 / (45 + SEL[6:0])

SEL[6:0] = 67 to 127: 3/7 V/V
SEL[6:0] = 66: 16/37 V/V
...
SEL[6:0] = 35: 3/5 V/V
...
SEL[6:0] = 5: 24/25 V/V
SEL[6:0] = 4: 48/49 V/V
SEL[6:0] = 1 to 3: 1 V/V
SEL[6:0] = 0 (EN signal low) 		RW 0x00

Table 45. EXTCTRL_SR_REG

Address Offset 0x29
Physical Address Instance (RESET DOMAIN: TURN OFF RESET)
Description EXTCTRL voltage selection register.
This register can be accessed by both control-dedicated and voltage-scaling-dedicated I2C interfaces depending on the SR_CTL_I2C_SEL register bit value.
Type RW

7 6 5 4 3 2 1 0
Reserved SEL

BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved RO 0
6:0 SEL Resistive divider ratio selection (4 EEPROM bits):
For SEL[6:0] = 3 to 67,
Ratio = 48 / (45 + SEL[6:0])

SEL[6:0] = 67 to 127: 3/7 V/V
SEL[6:0] = 66: 16/37 V/V
...
SEL[6:0] = 35: 3/5 V/V
...
SEL[6:0] = 5: 24/25 V/V
SEL[6:0] = 4: 48/49 V/V
SEL[6:0] = 1 to 3: 1 V/V
SEL[6:0] = 0 (EN signal low) 		RW 0x03

Table 46. LDO1_REG

Address Offset 0x30
Physical Address Instance (RESET DOMAIN: TURNOFF OFF RESET)
Description LDO1 regulator control register
Type RW

7 6 5 4 3 2 1 0
SEL ST

BITS FIELD NAME DESCRIPTION TYPE RESET
7:2 SEL Supply voltage (EEPROM bits):
SEL[7:2] = 00000: 000011: 1 V
SEL[7:2] = 000100: 1 V
SEL[7:2] = 000101: 1.05 V
...
SEL[7:2] = 110001: 3.25 V
SEL[7:2] = 110010: 3.3 V
(Default value: See boot configuration)		 RW 0x0
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 47. LDO2_REG

Address Offset 0x31
Physical Address Instance (RESET DOMAIN: TURNOFF OFF RESET)
Description LDO2 regulator control register
Type RW

7 6 5 4 3 2 1 0
SEL ST

BITS FIELD NAME DESCRIPTION TYPE RESET
7:2 SEL Supply voltage (EEPROM bits):
SEL[7:2] = 00000: 000011: 1 V
SEL[7:2] = 000100: 1 V
SEL[7:2] = 000101: 1.05 V
...
SEL[7:2] = 110001: 3.25 V
SEL[7:2] = 110010: 3.3 V
(Default value: See boot configuration)		 RW 0x0
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 48. LDO5_REG

Address Offset 0x32
Physical Address Instance (RESET DOMAIN: TUROFF RESET)
Description LDO5 regulator control register
Type RW

7 6 5 4 3 2 1 0
Reserved SEL ST

BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved RO
R returns 0s 		0
6:2 SEL Supply voltage (EEPROM bits):
SEL[6:2] = 00000: 1 V
SEL[6:2] = 00001: 1 V
SEL[6:2] = 00010: 1 V
SEL[6:2] = 00011: 1.1 V
...
SEL[6:2] = 11000: 3.2 V
SEL[6:2] = 11001: 3.3 V
(Default value: See boot configuration)		 RW 0x00
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 49. LDO8_REG

Address Offset 0x33
Physical Address Instance (RESET DOMAIN: TURNOFF OFF RESET)
Description LDO8 regulator control register
Type RW

7 6 5 4 3 2 1 0
Reserved SEL ST

BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved RO
R returns 0s 		0
6:2 SEL Supply voltage (EEPROM bits):
SEL[6:2] = 00000: 1 V
SEL[6:2] = 00001: 1 V
SEL[6:2] = 00010: 1 V
SEL[6:2] = 00011: 1.1 V
...
SEL[6:2] = 11000: 3.2 V
SEL[6:2] = 11001: 3.3 V
(Default value: See boot configuration)		 RW 0x00
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 50. LDO7_REG

Address Offset 0x34
Physical Address Instance (RESET DOMAIN: TURNOFF OFF RESET)
Description LDO7 regulator control register
Type RW

7 6 5 4 3 2 1 0
Reserved SEL ST

BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved RO
R returns 0s 		0
6:2 SEL Supply voltage (EEPROM bits):
SEL[6:2] = 00000: 1 V
SEL[6:2] = 00001: 1 V
SEL[6:2] = 00010: 1 V
SEL[6:2] = 00011: 1.1 V
...
SEL[6:2] = 11000: 3.2 V
SEL[6:2] = 11001: 3.3 V
(Default value: See boot configuration)		 RW 0x00
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 51. LDO6_REG

Address Offset 0x35
Physical Address Instance (RESET DOMAIN: TURNOFF OFF RESET)
Description LDO6 regulator control register
Type RW

7 6 5 4 3 2 1 0
Reserved SEL ST

BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved RO
R returns 0s 		0
6:2 SEL Supply voltage (EEPROM bits):
SEL[6:2] = 00000: 1 V
SEL[6:2] = 00001: 1 V
SEL[6:2] = 00010: 1 V
SEL[6:2] = 00011: 1.1 V
...
SEL[6:2] = 11000: 3.2 V
SEL[6:2] = 11001: 3.3 V
(Default value: See boot configuration)		 RW 0x00
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 52. LDO4_REG

Address Offset 0x36
Physical Address Instance (RESET DOMAIN: TURNOFF OFF RESET)
Description LDO4 regulator control register
Type RW

7 6 5 4 3 2 1 0
SEL ST

BITS FIELD NAME DESCRIPTION TYPE RESET
7:2 SEL Supply voltage (EEPROM bits):
SEL[7:2] = 00000: 00000: 0.8 V
SEL[7:2] = 00000: 000001: 0.85 V
SEL[7:2] = 00000: 000010: 0.9 V
SEL[7:2] = 000100: 1 V
SEL[7:2] = 000101: 1.05 V
...
SEL[7:2] = 110001: 3.25 V
SEL[7:2] = 110010: 3.3 V
Applicable voltage selection
TRACK LDO 0: 1 V to 3.3 V
TRACK LDO 1: 0.8 V to 1.5 V
(Default value: See boot configuration)		 RW 0x00
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 53. LDO3_REG

Address Offset 0x37
Physical Address Instance (RESET DOMAIN: TURNOFF OFF RESET)
Description LDO3 regulator control register
Type RW

7 6 5 4 3 2 1 0
Reserved SEL ST

BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved RO
R returns 0s 		0
6:2 SEL Supply voltage (EEPROM bits):
SEL[6:2] = 00000: 1 V
SEL[6:2] = 00001: 1 V
SEL[6:2] = 00010: 1 V
SEL[6:2] = 00011: 1.1 V
...
SEL[6:2] = 11000: 3.2 V
SEL[6:2] = 11001: 3.3 V
(Default value: See boot configuration)		 RW 0x00
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 54. Therm_REG

Address Offset 0x38
Physical Address Instance (RESET DOMAIN:
Description Thermal control register bits[5:2}: GENERAL RESET
Type RW bit[0] TURNOFF OFF RESET)

7 6 5 4 3 2 1 0
Reserved THERM_HD THERM_TS THERM_HDSEL Reserved THERM_STATE

BITS FIELD NAME DESCRIPTION TYPE RESET
7:6 Reserved Reserved bit RO
R returns 0s 		0x0
5 THERM_HD Hot die detector output:
When set to 0: the hot die threshold is not reached
When set to 1: the hot die threshold is reached 		RO 0
4 THERM_TS Thermal shutdown detector output:
When set to 0: the thermal shutdown threshold is not reached
When set to 1: the thermal shutdown threshold is reached 		RO 0
3:2 THERM_HDSEL Temperature selection for hot-die detector:
When set to 00: Low temperature threshold
…
When set to 11: High temperature threshold 		RW 0x3
1 Reserved RO
R returns 0s 		0
0 THERM_STATE Thermal shutdown module enable signal:
When set to 0: thermal shutdown module is disable
When set to 1: thermal shutdown module is enable 		RW 1

Table 55. BBCH_REG

Address Offset 0x39
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description Back-up battery charger control register
Type RW

7 6 5 4 3 2 1 0
Reserved BBSEL BBCHEN

BITS FIELD NAME DESCRIPTION TYPE RESET
7:3 Reserved Reserved bit RO
R returns 0s 		0x00
2:1 BBSEL Back up battery charge voltage selection:
BBSEL[1:0] = 00: 3 V
BBSEL[1:0] = 01: 2.52 V
BBSEL[1:0] = 10: 3.15 V
BBSEL[1:0] = 11: VBAT 		RW 0x0
0 BBCHEN Back up battery charge enable RW 0

Table 56. DCDCCTRL_REG

Address Offset 0x3E
Physical Address Instance RESET DOMAIN:
bits [7:3]: TURNOFF OFF RESET
bits [2:0]: GENERAL RESET
Description DCDC control register
Type RW

7 6 5 4 3 2 1 0
Reserved TRACK VDD2_PSKIP VDD1_PSKIP VIO_PSKIP DCDCCKEXT DCDCCKSYNC

BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved Reserved bit RO
R returns 0s 		0
6 TRACK 1: Tracking mode: LDO4 output follows VDD1 setting when VDD1 active. See the Functional Registers section for more information. RW 0
0: Normal LDO operation without tracking
5 VDD2_PSKIP VDD2 pulse skip mode enable (EEPROM bit)
Default value: See boot configuration		 RW 1
4 VDD1_PSKIP VDD1 pulse skip mode enable (EEPROM bit)
Default value: See boot configuration		 RW 1
3 VIO_PSKIP VIO pulse skip mode enable (EEPROM bit)
Default value: See boot configuration		 RW 1
2 DCDCCKEXT This signal control the muxing of the GPIO2 pad:
When set to 0: this pad is a GPIO
When set to 1: this pad is used as input for an external clock used for the synchronization of the DCDCs 		RW 0
1:0 DCDCCKSYNC DC-DC clock configuration:
DCDCCKSYNC[1:0] = 00: no synchronization of DCDC clocks
DCDCCKSYNC[1:0] = 01: DCDC synchronous clock with phase shift
DCDCCKSYNC[1:0] = 10: no synchronization of DCDC clocks
DCDCCKSYNC[1:0] = 11: DCDC synchronous clock 		RW 0x1

Table 57. DEVCTRL_REG

Address Offset 0x3F
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description Device control register
Type RW

7 6 5 4 3 2 1 0
PWR_OFF_SEQ RTC_PWDN CK32K_CTRL SR_CTL_I2C_SEL DEV_OFF_RST DEV_ON DEV_SLP DEV_OFF

BITS FIELD NAME DESCRIPTION TYPE RESET
7 PWR_OFF_SEQ When set to 1, power-off is sequential, reverse of power-on sequence (first resource to power on is the last to power off).
When set to 0, all resources disabled at the same time		 RW 0
6 RTC_PWDN When set to 1, disable the RTC digital domain (clock gating and reset of RTC registers and logic).
This register bit is not reset in BACKUP state.		 RW 0
5 CK32K_CTRL Internal 32-kHz clock source control bit (EEPROM bit):
When set to 0, either the crystal oscillator or the external clock is used as the internal 32-kHz clock source
When set to set to 1, the internal RC oscillator is used as the 32-kHz clock source. 		RW 0
4 SR_CTL_I2C_SEL Voltage scaling registers access control bit:
When set to 0: access to registers by voltage scaling I2C
When set to 1: access to registers by control I2C. The voltage scaling registers are: VDD1_OP_REG, VDD1_SR_REG, VDD2_OP_REG, VDD2_SR_REG, EXTCTRL_OP_REG, and EXTCTRL_SR_REG. 		RW 1
3 DEV_OFF_RST Writing 1 starts an ACTIVE-to-OFF or SLEEP-to-OFF device state transition (switch-off event) and activate reset of the digital core.
This bit is cleared in OFF state.		 RW 0
2 DEV_ON Writing 1 maintains the device on (ACTIVE or SLEEP device state) (if DEV_OFF = 0 and DEV_OFF_RST = 0).
EEPROM bit
(Default value: See boot configuration)		 RW 0
1 DEV_SLP Writing 1 allows SLEEP device state (if DEV_OFF = 0 and DEV_OFF_RST = 0).
Writing 0 starts an SLEEP-to-ACTIVE device state transition (wake-up event) (if DEV_OFF = 0 and DEV_OFF_RST = 0). This bit is cleared in OFF state. 		RW 0
0 DEV_OFF Writing 1 starts an ACTIVE-to-OFF or SLEEP-to-OFF device state transition (switch-off event). This bit is cleared in OFF state. RW 0

Table 58. DEVCTRL2_REG

Address Offset 0x40
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description Device control register
Type RW

7 6 5 4 3 2 1 0
Reserved DCDC_SLEEP_LVL TSLOT_LENGTH SLEEPSIG_POL PWON_LP_OFF PWON_LP_RST IT_POL

BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved RO
R returns 0s 		0
6 DCDC_SLEEP_LVL When set to 1, DCDC output level in SLEEP mode is VDDx_SR_REG, to be other than 0 V.
When set to 0, no effect		 RW 0
5:4 TSLOT_LENGTH Time slot duration programming (EEPROM bit):
When set to 00: 0 µs
When set to 01: 200 µs
When set to 10: 500 µs
When set to 11: 2 ms
(Default value: See boot configuration)		 RW 0x3
3 SLEEPSIG_POL When set to 1, SLEEP signal active-high
When set to 0, SLEEP signal active-low 		RW 0
2 PWON_LP_OFF When set to 1, allows device turn-off after a PWON Long Press (signal low) (EEPROM bits).
(Default value: See boot configuration)		 RW 1
1 PWON_LP_RST When set to 1, allows digital core reset when the device is OFF (EEPROM bit).
(Default value: See boot configuration)		 RW 0
0 IT_POL INT1 interrupt pad polarity control signal (EEPROM bit):
When set to 0, active low
When set to 1, active high
(Default value: See boot configuration)		 RW 0

Table 59. SLEEP_KEEP_LDO_ON_REG

Address Offset 0x41
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description When corresponding control bit = 0 in EN1_ LDO_ASS register (default setting): Configuration Register keeping the full load capability of LDO regulator (ACTIVE mode) during the SLEEP state of the device.
When control bit = 1, LDO regulator full load capability (ACTIVE mode) is maintained during device SLEEP state.
When control bit = 0, the LDO regulator is set or stay in low-power mode during device SLEEP state(but then supply state can be overwritten programming ST[1:0]). There is no control bit value effect if the LDO regulator is off.
When corresponding control bit = 1 in EN1_ LDO_ASS register: Configuration register setting the LDO regulator state driven by SCLSR_EN1 signal low level (when SCLSR_EN1 is high the regulator is on, full power):
- the regulator is set off if the corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register (default)
- the regulator is set in low-power mode if its corresponding control bit = 1 in SLEEP_KEEP_LDO_ON register
Type RW

7 6 5 4 3 2 1 0
LDO3_KEEPON LDO4_KEEPON LDO7_KEEPON LDO8_KEEPON LDO5_KEEPON LDO2_KEEPON LDO1_KEEPON LDO6_KEEPON

BITS FIELD NAME DESCRIPTION TYPE RESET
7 LDO3_KEEPON Setting supply state during device SLEEP state or when SCLSR_EN1 is low RW 0
6 LDO4_KEEPON Setting supply state during device SLEEP state or when SCLSR_EN1 is low RW 0
5 LDO7_KEEPON Setting supply state during device SLEEP state or when SCLSR_EN1 is low RW 0
4 LDO8_KEEPON Setting supply state during device SLEEP state or when SCLSR_EN1 is low RW 0
3 LDO5_KEEPON Setting supply state during device SLEEP state or when SCLSR_EN1 is low RW 0
2 LDO2_KEEPON Setting supply state during device SLEEP state or when SCLSR_EN1 is low RW 0
1 LDO1_KEEPON Setting supply state during device SLEEP state or when SCLSR_EN1 is low RW 0
0 LDO6_KEEPON Setting supply state during device SLEEP state or when SCLSR_EN1 is low RW 0

Table 60. SLEEP_KEEP_RES_ON_REG

Address Offset 0x42
Physical Address Instance
Description Configuration Register keeping, during the SLEEP state of the device (but then supply state can be overwritten programming ST[1:0]):
- the full load capability of LDO regulator (ACTIVE mode),
- The PWM mode of DC-DC converter
- 32-kHz clock output
- Register access though I2C interface (keeping the internal high speed clock on)
- Die thermal monitoring is on
There is no control bit value effect if the resource is off.
Type RW

7 6 5 4 3 2 1 0
THERM_KEEPON CLKOUT32K_KEEPON VRTC_KEEPON I2CHS_KEEPON Reserved VDD2_KEEPON VDD1_KEEPON VIO_KEEPON

BITS FIELD NAME DESCRIPTION TYPE RESET
7 THERM_KEEPON When set to 1, thermal monitoring is maintained during device SLEEP state.
When set to 0, thermal monitoring is turned off during device SLEEP state. 		RW 0
6 CLKOUT32K_KEEPON When set to 1, CLK32KOUT output is maintained during device SLEEP state.
When set to 0, CLK32KOUT output is set low during device SLEEP state. 		RW 0
5 VRTC_KEEPON When set to 1, LDO regulator full load capability (ACTIVE mode) is maintained during device SLEEP state.
When set to 0, the LDO regulator is set or stays in low-power mode during device SLEEP state. 		RW 0
4 I2CHS_KEEPON When set to 1, high speed internal clock is maintained during device SLEEP state.
When set to 0, high speed internal clock is turned off during device SLEEP state. 		RW 0
3 Reserved RO 0
2 VDD2_KEEPON When set to 1, VDD2 SMPS-PWM mode is maintained during device SLEEP state. No effect if VDD2 working mode is PFM.
When set to 0, VDD2 SMPS-PFM mode is set during device SLEEP state. 		RW 0
1 VDD1_KEEPON When set to 1, VDD1 SMPS-PWM mode is maintained during device SLEEP state. No effect if VDD1 working mode is PFM.
When set to 0, VDD1 SMPS-PFM mode is set during device SLEEP state. 		RW 0
0 VIO_KEEPON When set to 1, VIO SMPS-PWM mode is maintained during device SLEEP state. No effect if VIO working mode is PFM.
When set to 0, VIO SMPS-PFM mode is set during device SLEEP state. 		RW 0

Table 61. SLEEP_SET_LDO_OFF_REG

Address Offset 0x43
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description Configuration register turning-off LDO regulator during the SLEEP state of the device.
Corresponding *_KEEP_ON control bit in SLEEP_KEEP_RES_ON register should be 0 to make this *_SET_OFF control bit effective
Type RW

7 6 5 4 3 2 1 0
LDO3_SETOFF LDO4_SETOFF LDO7_SETOFF LDO8_SETOFF LDO5_SETOFF LDO2_SETOFF LDO1_SETOFF LDO6_SETOFF

BITS FIELD NAME DESCRIPTION TYPE RESET
7 LDO3_SETOFF When set to 1, LDO regulator is turned off during device SLEEP state.
When set to 0, No effect		 RW 0
6 LDO4_SETOFF When set to 1, LDO regulator is turned off during device SLEEP state.
When set to 0, No effect		 RW 0
5 LDO7_SETOFF When set to 1, LDO regulator is turned off during device SLEEP state.
When set to 0, No effect		 RW 0
4 LDO8_SETOFF When set to 1, LDO regulator is turned off during device SLEEP state.
When set to 0, No effect		 RW 0
3 LDO5_SETOFF When set to 1, LDO regulator is turned off during device SLEEP state.
When set to 0, No effect		 RW 0
2 LDO2_SETOFF When set to 1, LDO regulator is turned off during device SLEEP state.
When set to 0, No effect		 RW 0
1 LDO1_SETOFF When set to 1, LDO regulator is turned off during device SLEEP state.
When set to 0, No effect		 RW 0
0 LDO6_SETOFF When set to 1, LDO regulator is turned off during device SLEEP state.
When set to 0, No effect		 RW 0

Table 62. SLEEP_SET_RES_OFF_REG

Address Offset 0x44
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description Configuration Register turning-off SMPS regulator during the SLEEP state of the device.
Corresponding *_KEEP_ON control bit in SLEEP_KEEP_RES_ON2 register should be 0 to make this *_SET_OFF control bit effective. Supplies voltage expected after the wake-up (SLEEP-to-ACTIVE state transition) can also be programmed.
Type RW

7 6 5 4 3 2 1 0
DEFAULT_VOLT Reserved SPARE_SETOFF EXTCTRL_SETOFF VDD2_SETOFF VDD1_SETOFF VIO_SETOFF

BITS FIELD NAME DESCRIPTION TYPE RESET
7 DEFAULT_VOLT When set to 1, default voltages (register value after switch-on) are applied to all resources during SLEEP-to-ACTIVE transition.
When set to 0, voltages programmed before the ACTIVE-to-SLEEP state transition are used to turned-on supplies during SLEEP-to-ACTIVE state transition.		 RW 0
6:5 Reserved RO
R returns 0s 		0x0
4 SPARE_SETOFF Spare bit RW 0
3 EXTCTRL_SETOFF When set to 1, SMPS is turned off during device SLEEP state.
When set to 0, No effect.		 RW 0
2 VDD2_SETOFF When set to 1, SMPS is turned off during device SLEEP state.
When set to 0, No effect.		 RW 0
1 VDD1_SETOFF When set to 1, SMPS is turned off during device SLEEP state.
When set to 0, No effect.		 RW 0
0 VIO_SETOFF When set to 1, SMPS is turned off during device SLEEP state.
When set to 0, No effect.		 RW 0

Table 63. EN1_LDO_ASS_REG

Address Offset 0x45
Physical Address Instance (RESET DOMAIN: TURNOFF RESET)
Description Configuration Register setting the LDO regulators, driven by the multiplexed SCLSR_EN1 signal.
When control bit = 1, LDO regulator state is driven by the SCLSR_EN1 control signal and is also defined though SLEEP_KEEP_LDO_ON register setting:
When SCLSR_EN1 is high the regulator is on,
When SCLSR_EN1 is low:
- the regulator is off if the corresponding control bit = 0 in SLEEP_KEEP_LDO_ON register
- the regulator is working in low-power mode if the corresponding control bit = 1 in
SLEEP_KEEP_LDO_ON register
When control bit = 0 no effect: LDO regulator state is driven though registers programming and the device state
Any control bit of this register set to 1 disables the I2C SR Interface functionality
Type RW

7 6 5 4 3 2 1 0
LDO3_EN1 LDO4_EN1 LDO7_EN1 LDO8_EN1 LDO5_EN1 LDO2_EN1 LDO1_EN1 LDO6_EN1

BITS FIELD NAME DESCRIPTION TYPE RESET
7 LDO3_EN1 Setting supply-state control though the SCLSR_EN1 signal RW 0
6 LDO4_EN1 Setting supply-state control though the SCLSR_EN1 signal RW 0
5 LDO7_EN1 Setting supply-state control though the SCLSR_EN1 signal RW 0
4 LDO8_EN1 Setting supply-state control though the SCLSR_EN1 signal RW 0
3 LDO5_EN1 Setting supply-state control though the SCLSR_EN1 signal RW 0
2 LDO2_EN1 Setting supply-state control though the SCLSR_EN1 signal RW 0
1 LDO1_EN1 Setting supply-state control though the SCLSR_EN1 signal RW 0
0 LDO6_EN1 Setting supply-state control though the SCLSR_EN1 signal RW 0

Table 64. EN1_SMPS_ASS_REG

Address Offset 0x46
Physical Address Instance (RESET DOMAIN: TURNOFF RESET)
Description Configuration register setting the SMPS supplies driven by the multiplexed SCLSR_EN1 signal.
When control bit = 1, SMPS supply state and voltage is driven by the SCLSR_EN1 control signal and is also defined though SLEEP_KEEP_RES_ON register setting.
When control bit = 0 no effect: SMPS Supply state is driven though registers programming and the device state.
Any control bit of this register set to 1 disables the I2C SR Interface functionality
Type RW

7 6 5 4 3 2 1 0
Reserved SPARE_EN1 EXTCTRL_EN1 VDD2_EN1 VDD1_EN1 VIO_EN1

BITS FIELD NAME DESCRIPTION TYPE RESET
7:5 Reserved RO
R returns 0s		 0x0
4 SPARE_EN1 Spare bit RW 0
3 EXTCTRL_EN1 When control bit = 1:
When EN1 is high the supply voltage is programmed though EXTCTRL_OP_REG register, and it can also be programmed off.
When EN1 is low the supply voltage is programmed though EXTCTRL_SR_REG register, and it can also be programmed off.
When control bit = 0: No effect: Supply state is driven though registers programming and the device state		 RW 0
2 VDD2_EN1 When control bit = 1:
When SCLSR_EN1 is high the supply voltage is programmed though VDD2_OP_REG register, and it can also be programmed off.
When SCLSR_EN1 is low the supply voltage is programmed though VDD2_SR_REG register, and it can also be programmed off.
When SCLSR_EN1 is low and SLEEP_KEEP_RES_ON = 1 the SMPS is working in low-power mode, if not tuned off through VDD2_SR_REG register.
When control bit = 0 No effect: the supply state is driven though registers programming and the device state		 RW 0
1 VDD1_EN1 When 1:
When SCLSR_EN1 is high the supply voltage is programmed though VDD1_OP_REG register, and it can also be programmed off.
When SCLSR_EN1 is low the supply voltage is programmed though VDD1_SR_REG register, and it can also be programmed off.
When SCLSR_EN1 is low and SLEEP_KEEP_RES_ON = 1 the SMPS is working in low-power mode, if not tuned off though VDD1_SR_REG register.
When control bit = 0 no effect: supply state is driven though registers programming and the device state		 RW 0
0 VIO_EN1 When control bit = 1, the supply state is driven by the SCLSR_EN1 control signal and is also defined though the SLEEP_KEEP_RES_ON register setting:
When SCLSR_EN1 is high the supply is on,
When SCLSR_EN1 is low:
- the supply is off (default) or the SMPS is working in low-power mode if the corresponding control bit = 1 in SLEEP_KEEP_RES_ON register
When control bit = 0 No effect: SMPS state is driven though registers programming and the device state		 RW 0

Table 65. EN2_LDO_ASS_REG

Address Offset 0x47
Physical Address Instance (RESET DOMAIN: TURNOFF RESET)
Description Configuration Register setting the LDO regulators, driven by the multiplexed SDASR_EN2 signal.
When control bit = 1, LDO regulator state is driven by the SDASR_EN2 control signal and is also defined though SLEEP_KEEP_LDO_ON register setting:
When SDASR_EN2 is high the regulator is on,
When SCLSR_EN2 is low:
- the regulator is off if the corresponding control bit = 0 in SLEEP_KEEP_LDO_ON register
- the regulator is working in low-power mode if the corresponding control bit = 1 in SLEEP_KEEP_LDO_ON register
When control bit = 0 no effect: LDO regulator state is driven though registers programming and the device state
Any control bit of this register set to 1 disables the I2C SR Interface functionality
Type RW

7 6 5 4 3 2 1 0
LDO3_EN2 LDO4_EN2 LDO7_EN2 LDO8_EN2 LDO5_EN2 LDO2_EN2 LDO1_EN2 LDO6_EN2

BITS FIELD NAME DESCRIPTION TYPE RESET
7 LDO3_EN2 Setting supply-state control though the SDASR_EN2 signal RW 0
6 LDO4_EN2 Setting supply-state control though the SDASR_EN2 signal RW 0
5 LDO7_EN2 Setting supply-state control though the SDASR_EN2 signal RW 0
4 LDO8_EN2 Setting supply-state control though the SDASR_EN2 signal RW 0
3 LDO5_EN2 Setting supply-state control though the SDASR_EN2 signal RW 0
2 LDO2_EN2 Setting supply-state control though the SDASR_EN2 signal RW 0
1 LDO1_EN2 Setting supply-state control though the SDASR_EN2 signal RW 0
0 LDO6_EN2 Setting supply-state control though the SDASR_EN2 signal RW 0

Table 66. EN2_SMPS_ASS_REG

Address Offset 0x48
Physical Address Instance (RESET DOMAIN: TURNOFF RESET)
Description Configuration Register setting the SMPS Supplies driven by the multiplexed SDASR_EN2 signal.
When control bit = 1, the SMPS Supply state and voltage is driven by the SDASR_EN2 control signal and is also defined though SLEEP_KEEP_RES_ON register setting.
When control bit = 0 no effect: the SMPS Supply state is driven though registers programming and the device state
Any control bit of this register set to 1 disables the I2C SR Interface functionality
Type RW

7 6 5 4 3 2 1 0
Reserved SPARE_EN2 EXTCTRL_EN2 VDD2_EN2 VDD1_EN2 VIO_EN2

BITS FIELD NAME DESCRIPTION TYPE RESET
7:5 Reserved RO
R returns 0s 		0x0
4 SPARE_EN2 Spare bit RW 0
3 EXTCTRL_EN2 When control bit = 1:
When EN2 is high the supply voltage is programmed though EXTCTRL_OP_REG register, and it can also be programmed off..
When EN2 is low the supply voltage is programmed though EXTCTRL_SR_REG register, and it can also be programmed off.
When EN2 is low and EXTCTRL_KEEPON = 1 the SMPS is working in low-power mode, if not tuned off though EXTCTRL_SR_REG register.
When control bit = 0 no effect: the supply state is driven though registers programming and the device state		 RW 0
2 VDD2_EN2 When control bit = 1:
When SDASR_EN2 is high the supply voltage is programmed though VDD2_OP_REG register, and it can also be programmed off.
When SDASR_EN2 is low the supply voltage is programmed though VDD2_SR_REG register, and it can also be programmed off.
When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 1 the SMPS is working in low-power mode, if not tuned off though VDD2_SR_REG register.
When control bit = 0 no effect: the supply state is driven though registers programming and the device state		 RW 0
1 VDD1_EN2 When control bit = 1:
When SDASR_EN2 is high the supply voltage is programmed though VDD1_OP_REG register, and it can also be programmed off.
When SDASR_EN2 is low the supply voltage is programmed though VDD1_SR_REG register, and it can also be programmed off.
When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 1 the SMPS is working in low-power mode, if not tuned off though VDD1_SR_REG register.
When control bit = 0 no effect: the supply state is driven though registers programming and the device state		 RW 0
0 VIO_EN2 When control bit = 1,
supply state is driven by the SCLSR_EN2 control signal and is also defined though SLEEP_KEEP_RES_ON register setting:
When SDASR _EN2 is high the supply is on,
When SDASR _EN2 is low :
- the supply is off (default) or the SMPS is working in low-power mode if its corresponding control bit = 1 in SLEEP_KEEP_RES_ON register
When control bit = 0 no effect: the SMPS state is driven though registers programming and the device state		 RW 0

Table 67. INT_STS_REG

Address Offset 0x50
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. The interrupt-status bit is cleared by writing 1.
Type RW

7 6 5 4 3 2 1 0
RTC_PERIOD_IT RTC_ALARM_IT HOTDIE_IT PWRHOLD_R_IT PWRON_LP_IT PWRON_IT Reserved PWRHOLD_F_IT

BITS FIELD NAME DESCRIPTION TYPE RESET
7 RTC_PERIOD_IT RTC-period-event interrupt status RW
W1 to Clr 		0
6 RTC_ALARM_IT RTC-alarm-event interrupt status RW
W1 to Clr 		0
5 HOTDIE_IT Hot-die-event interrupt status RW
W1 to Clr 		0
4 PWRHOLD_R_IT Rising-PWRHOLD-event interrupt status RW
W1 to Clr 		0
3 PWRON_LP_IT PWRON-long-press event interrupt status RW
W1 to Clr 		0
2 PWRON_IT PWRON-event interrupt status RW
W1 to Clr 		0
1 Reserved Reserved, always clear RW
W1 to Clr 		0
0 PWRHOLD_F_IT Falling-PWRHOLD-event interrupt status RW
W1 to Clr 		0

Table 68. INT_MSK_REG

Address Offset 0x51
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is updated.
Type RW

7 6 5 4 3 2 1 0
RTC_PERIOD_IT_MSK RTC_ALARM_IT_MSK HOTDIE_IT_MSK PWRHOLD_R_IT_MSK PWRON_LP_IT_MSK PWRON_IT_MSK Reserved PWRHOLD_F_IT_MSK

BITS FIELD NAME DESCRIPTION TYPE RESET
7 RTC_PERIOD_IT_MSK RTC-period-event interrupt mask RW 1
6 RTC_ALARM_IT_MSK RTC-alarm-event interrupt mask RW 1
5 HOTDIE_IT_MSK Hot-die-event interrupt mask RW 1
4 PWRHOLD_R_IT_MSK PWRHOLD rising-edge-event interrupt mask RW 1
3 PWRON_LP_IT_MSK PWRON long-press-event interrupt mask RW 1
2 PWRON_IT_MSK PWRON-event interrupt mask RW 1
1 Reserved Reserved, always masks RW 1
0 PWRHOLD_F_IT_MSK PWRHOLD falling-edge-event interrupt mask RW 1

Table 69. INT_STS2_REG

Address Offset 0x52
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is cleared by writing 1.
Type RW

7 6 5 4 3 2 1 0
GPIO3_F_IT GPIO3_R_IT GPIO2_F_IT GPIO2_R_IT GPIO1_F_IT GPIO1_R_IT GPIO0_F_IT GPIO0_R_IT

BITS FIELD NAME DESCRIPTION TYPE RESET
7 GPIO3_F_IT GPIO3 falling-edge-detection interrupt status RW
W1 to Clr 		0
6 GPIO3_R_IT GPIO3 rising-edge-detection interrupt status RW
W1 to Clr 		0
5 GPIO2_F_IT GPIO2 falling-edge-detection interrupt status RW
W1 to Clr 		0
4 GPIO2_R_IT GPIO2 rising-edge-detection interrupt status RW
W1 to Clr 		0
3 GPIO1_F_IT GPIO1 falling-edge-detection interrupt status RW
W1 to Clr 		0
2 GPIO1_R_IT GPIO1 rising-edge-detection interrupt status RW
W1 to Clr 		0
1 GPIO0_F_IT GPIO0 falling-edge-detection interrupt status RW
W1 to Clr 		0
0 GPIO0_R_IT GPIO0 rising-edge-detection interrupt status RW
W1 to Clr 		0

Table 70. INT_MSK2_REG

Address Offset 0x53
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is updated.
Type RW

7 6 5 4 3 2 1 0
GPIO3_F_IT_MSK GPIO3_R_IT_MSK GPIO2_F_IT_MSK GPIO2_R_IT_MSK GPIO1_F_IT_MSK GPIO1_R_IT_MSK GPIO0_F_IT_MSK GPIO0_R_IT_MSK

BITS FIELD NAME DESCRIPTION TYPE RESET
7 GPIO3_F_IT_MSK GPIO3 falling-edge-detection interrupt mask RW 1
6 GPIO3_R_IT_MSK GPIO3 rising-edge-detection interrupt mask RW 1
5 GPIO2_F_IT_MSK GPIO2 falling-edge-detection interrupt mask RW 1
4 GPIO2_R_IT_MSK GPIO2 rising-edge-detection interrupt mask RW 1
3 GPIO1_F_IT_MSK GPIO1 falling-edge-detection interrupt mask RW 1
2 GPIO1_R_IT_MSK GPIO1 rising-edge-detection interrupt mask RW 1
1 GPIO0_F_IT_MSK GPIO0 falling-edge-detection interrupt mask RW 1
0 GPIO0_R_IT _MSK GPIO0 rising-edge-detection interrupt mask RW 1

Table 71. INT_STS3_REG

Address Offset 0x54
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. The interrupt-status bit is cleared by writing 1.
Type RW

7 6 5 4 3 2 1 0
PWRDN_IT Reserved Reserved WTCHDG_IT GPIO5_F_IT GPIO5_R_IT GPIO4_F_IT GPIO4_R_IT

BITS FIELD NAME DESCRIPTION TYPE RESET
7 PWRDN_IT PWRDN reset input high detected RW
W1 to Clr 		0
6 Reserved Always clear RW
W1 to Clr 		0
5 Reserved Always clear RW
W1 to Clr 		0
4 WTCHDG_IT Watchdog interrupt status RW
W1 to Clr 		0
3 GPIO5_F_IT GPIO5 falling-edge-detection interrupt status RW
W1 to Clr 		0
2 GPIO5_R_IT GPIO5 rising-edge-detection interrupt status RW
W1 to Clr 		0
1 GPIO4_F_IT GPIO4 falling-edge-detection interrupt status RW
W1 to Clr 		0
0 GPIO4_R_IT GPIO4 rising-edge-detection interrupt status RW
W1 to Clr 		0

Table 72. INT_MSK3_REG

Address Offset 0x55
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is updated.
Type RW

7 6 5 4 3 2 1 0
PWRDN_IT_MSK Reserved Reserved WTCHDG_IT_MSK GPIO5_F_IT_MSK GPIO5_R_IT_MSK GPIO4_F_IT_MSK GPIO4_R_IT_MSK

BITS FIELD NAME DESCRIPTION TYPE RESET
7 PWRDN_IT_MSK PWRDN interrupt mask RW 1
6 Reserved Always clear RW 1
5 Reserved Always clear RW 1
4 WTCHDG_IT_MSK Watchdog interrupt mask RW 1
3 GPIO5_F_IT_MSK GPIO5 falling-edge-detection interrupt mask RW 1
2 GPIO5_R_IT_MSK GPIO5 rising-edge-detection interrupt mask RW 1
1 GPIO4_F_IT_MSK GPIO4 falling-edge-detection interrupt mask RW 1
0 GPIO4_R_IT_MSK GPIO4 rising-edge-detection interrupt mask RW 1

Table 73. GPIO0_REG

Address Offset 0x60
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description GPIO0 configuration register
Type RW

7 6 5 4 3 2 1 0
GPIO_SLEEP Reserved GPIO_ODEN GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET

BITS FIELD NAME DESCRIPTION TYPE RESET
7 GPIO_SLEEP 1: as GPO, force low
0: No impact, keep as in active mode		 RW 0
6 Reserved Reserved bit RO
R returns 0s 		0
5 GPIO_ODEN Selection of output mode, EEPROM bit
0: Push-pull output
1: Open-drain output
(Default value: See boot configuration)
GPIO assigned to power-up sequence, this bit is set to 1 by a TURNOFF reset		 RW 0
4 GPIO_DEB GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to 1, the debouncing is 150 ms using a 50-ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 0
2 GPIO_CFG Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output
(Default value: See boot configuration)		 RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode
GPIO assigned to power-up sequence, this bit is in TURNOFF reset		 RW 0

Table 74. GPIO1_REG

Address Offset 0x61
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description GPIO1 configuration register
Type RW

7 6 5 4 3 2 1 0
Reserved GPIO_SEL GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET

BITS FIELD NAME DESCRIPTION TYPE RESET
7:6 Reserved RO
R returns 0s 		0x0
5 GPIO_SEL Select signal to be available at GPIO when configured as output:
0: GPIO_SET
1: LED1 out		 RW 0
4 GPIO_DEB GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to 1, the debouncing is 150 ms using a 50-ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1
2 GPIO_CFG Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output 		RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode RW 0

Table 75. GPIO2_REG

Address Offset 0x62
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description GPIO2 configuration register
Type RW

7 6 5 4 3 2 1 0
GPIO_SLEEP Reserved GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET

BITS FIELD NAME DESCRIPTION TYPE RESET
7 GPIO_SLEEP 1: as GPO, force low
0: no impact, keep as in active mode		 RW 0
6:5 Reserved RO
R returns 0s 		0x0
4 GPIO_DEB GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to 1, the debouncing is 150 ms using a 50-ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled
GPIO assigned to power-up sequence, this bit is set to 0 by a TURNOFF reset		 RW 1
2 GPIO_CFG Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output
(Default value: See boot configuration)
GPIO assigned to power-up sequence, this bit is set to 1 by a TURNOFF reset 		RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode
GPIO assigned to power-up sequence, this bit is in TURNOFF reset		 RW 0

Table 76. GPIO3_REG

Address Offset 0x63
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description GPIO3 configuration register
Type RW

7 6 5 4 3 2 1 0
Reserved GPIO_SEL GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET

BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved RO
R returns 0s 		0
6:5 GPIO_SEL Select signal to be available at GPIO when configured as output:
00: GPIO_SET
01: LED2 out
10: PWM out 		RW 0x0
4 GPIO_DEB GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to 1, the debouncing is 150 ms using a 50-ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1
2 GPIO_CFG Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output 		RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode RW 0

Table 77. GPIO4_REG

Address Offset 0x64
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description GPIO4 configuration register
Type RW

7 6 5 4 3 2 1 0
Reserved GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET

BITS FIELD NAME DESCRIPTION TYPE RESET
7:5 Reserved RO
R returns 0s 		0x0
4 GPIO_DEB GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to 1, the debouncing is 150 ms using a 50-ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1
2 GPIO_CFG Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output 		RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode RW 0

Table 78. GPIO5_REG

Address Offset 0x65
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description GPIO5 configuration register
Type RW

7 6 5 4 3 2 1 0
Reserved GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET

BITS FIELD NAME DESCRIPTION TYPE RESET
7:5 Reserved RO
R returns 0s 		0x0
4 GPIO_DEB GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to 1, the debouncing is 150 ms using a 50-ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1
2 GPIO_CFG Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output 		RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode RW 0

Table 79. GPIO6_REG

Address Offset 0x66
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description GPIO6 configuration register
Type RW

7 6 5 4 3 2 1 0
GPIO_SLEEP Reserved GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET

BITS FIELD NAME DESCRIPTION TYPE RESET
7 GPIO_SLEEP 1: as GPO, force low
0: no impact, keep as in active mode		 RW 0
6:5 Reserved RO
R returns 0s 		0x0
4 GPIO_DEB GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to 1, the debouncing is 150 ms using a 50-ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled
GPIO assigned to power-up sequence, this bit is set to 0 by a TURNOFF reset		 RW 1
2 GPIO_CFG Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output
(Default value: See boot configuration)
GPIO assigned to power-up sequence, this bit is set to 1 by a TURNOFF reset 		RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode
GPIO assigned to power-up sequence, this bit is in TURNOFF reset		 RW 0

Table 80. GPIO7_REG

Address Offset 0x67
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description GPIO7 configuration register
Type RW

7 6 5 4 3 2 1 0
GPIO_SLEEP Reserved GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET

BITS FIELD NAME DESCRIPTION TYPE RESET
7 GPIO_SLEEP 1: as GPO, force low
0: no impact, keep as is in active mode		 RW 0
6:5 Reserved RO
R returns 0s 		0x0
4 GPIO_DEB GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to1, the debouncing is 150 ms using a 50-ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown-control:
1: Pulldown is enabled
0: Pulldown is disabled
GPIO assigned to power-up sequence, this bit is set to 0 by a TURNOFF reset		 RW 1
2 GPIO_CFG Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output
(Default value: See boot configuration )
GPIO assigned to power-up sequence, this bit is set to 1 by a TURNOFF reset 		RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET The value set on the GPIO output when configured in output mode
GPIO assigned to power-up sequence, this bit is in TURNOFF reset		 RW 0

Table 81. GPIO8_REG

Address Offset 0x68
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description GPIO8 configuration register
Type RW

7 6 5 4 3 2 1 0
Reserved GPIO_SEL GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET

BITS FIELD NAME DESCRIPTION TYPE RESET
7:6 Reserved RO
R returns 0s 		0x0
5 GPIO_SEL Select signal to be available at GPIO when configured as output:
0: GPIO_SET
1: LED1 out		 RW 0
4 GPIO_DEB GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to 1, the debouncing is 150 ms using a 50-ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1
2 GPIO_CFG Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output 		RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode RW 0

Table 82. WATCHDOG_REG

Address Offset 0x69
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description Watchdog
Type RW

7 6 5 4 3 2 1 0
Reserved WTCHDG_MODE WTCHDG_TIME

BITS FIELD NAME DESCRIPTION TYPE RESET
7:4 Reserved RO
R returns 0s 		0x0
3 WTCHDG_MODE 0: Periodic operation:
A periodical interrupt is generated based on WTCHDG_TIME setting. The IC generates WTCHDOG shutdown if an interrupt is not cleared during the period.
1: Interrupt mode:
The IC generates WTCHDOG shutdown if an interrupt is pending (no cleared) more than WTCHDG_TIME s.		 RW 0
2:0 WTCHDG_TIME 000: Watchdog disabled
001: 5 seconds
010: 10 seconds
011: 20 Seconds
100: 40 seconds
101: 60 seconds
110: 80 seconds
111: 100 seconds (EEPROM bit)
(Default value: See boot configuration) 		RW 0x0

Table 83. BOOTSEQVER_REG

Address Offset 0x6A
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description Comparator control register
Type RW

7 6 5 4 3 2 1 0
Reserved BOOTSEQVER_SEL Reserved

BITS FIELD NAME DESCRIPTION TYPE RESET
7:6 Reserved RO
R returns 0s 		0x0
5:1 BOOTSEQVER_SEL EEPROM boot-sequence version RW 0x00
0 Reserved RO
R returns 0s 		0

Table 84. RESERVED

Address Offset 0x6B
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description Reserved
Type RW

7 6 5 4 3 2 1 0
Reserved Reserved VMBDCH2_DEB

BITS FIELD NAME DESCRIPTION TYPE RESET
7:6 Reserved RO
R returns 0s 		0x0
5:1 Reserved RW 0x00
0 Reserved RW 0

Table 85. LED_CTRL1_REG

Address Offset 0x6C
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description LED ON and OFF control register.
Type RW

7 6 5 4 3 2 1 0
Reserved LED2_PERIOD LED1_PERIOD

BITS FIELD NAME DESCRIPTION TYPE RESET
7:6 Reserved RO
R returns 0s 		0x0
5:3 LED2_PERIOD Period of LED2 signal:
000: LED2 OFF
001: 0.125 s
010: 0.25 s
...
110: 4 s
111: 8 s 		RW 0x0
2:0 LED1_PERIOD Period of LED1 signal:
000: LED1 OFF
001: 0.125 s
010: 0.25 s
...
10: 2 s
110: 4 s
111: 8 s 		RW 0x0

Table 86. LED_CTRL2_REG1

Address Offset 0x6D
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description LED ON and OFF control register.
Type RW

7 6 5 4 3 2 1 0
Reserved LED2_SEQ LED1_SEQ LED2_ON_TIME LED1_ON_TIME

BITS FIELD NAME DESCRIPTION TYPE RESET
7:6 Reserved RO
R returns 0s 		0x0
5 LED2_SEQ When set to 1, LED2 repeats two pulse sequences: ON (ON_TIME) - OFF (ON TIME) - ON (ON TIME) - OFF remainder of the period
When set to 0, LED2 generates one pulse: ON (ON_TIME) - OFF (ON TIME)) 		RW 0
4 LED1_SEQ When set to 1, LED1 repeats two pulse sequence: ON (ON_TIME) - OFF (ON TIME) - ON (ON TIME) - OFF remainder of the period.
When set to 0, LED1 generates one pulse: ON (ON_TIME) - OFF (ON TIME)) 		RW 0
3:2 LED2_ON_TIME LED2 ON time:
00: 62.5 ms
01: 125 ms
10: 250 ms
11: 500 ms 		RW 0x0
1:0 LED1_ON_TIME LED1 ON time:
00: 62.5 ms
01: 125 ms
10: 250 ms
11: 500 ms 		RW 0x0

Table 87. PWM_CTRL1_REG

Address Offset 0x6E
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description PWM frequency
Type RW

7 6 5 4 3 2 1 0
Reserved PWM_FREQ

BITS FIELD NAME DESCRIPTION TYPE RESET
7:2 Reserved Reserved bit RO
R returns 0s 		0x00
1:0 PWM_FREQ Frequency of PWM:
00: 500 Hz
01: 250 Hz
10: 125 Hz
11: 62.5 Hz 		RW 0x0

Table 88. PWM_CTRL2_REG

Address Offset 0x6F
Physical Address Instance (RESET DOMAIN: GENERAL RESET)
Description PWM duty cycle.
Type RW

7 6 5 4 3 2 1 0
FREQ_DUTY_CYCLE

BITS FIELD NAME DESCRIPTION TYPE RESET
7:0 FREQ_DUTY_CYCLE Duty cycle of PWM:
00000000: 0/256
...
11111111: 255/256 		RW 0x00

Table 89. SPARE_REG

Address Offset 0x70
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description Spare functional register
Type RW

7 6 5 4 3 2 1 0
SPARE

BITS FIELD NAME DESCRIPTION TYPE RESET
7:0 SPARE Spare bits RW 0x00

Table 90. VERNUM_REG

Address Offset 0x80
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description Silicon version number
Type RW

7 6 5 4 3 2 1 0
READ_BOOT Reserved VERNUM

BITS FIELD NAME DESCRIPTION TYPE RESET
7 READ_BOOT This bit enables the read of the BOOT mode in order to enter JTAG mode.
0: Disabled
1: Enabled		 RW 0
6:4 Reserved Reserved bit RO
R returns 0s		 0x0
3:0 VERNUM Value depending on silicon version number
0000 - Revision 1.0 		RO 0x0