SLVSCP3C January   2015  – July 2016 TPS7B4253-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Short Circuit and Overcurrent Protection
      2. 7.3.2 Integrated Inductive Clamp Protection
      3. 7.3.3 OUT Short to Battery and Reverse Polarity Protection
      4. 7.3.4 Undervoltage Shutdown
      5. 7.3.5 Thermal Protection
      6. 7.3.6 Regulated Output (OUT)
      7. 7.3.7 Enable (EN)
      8. 7.3.8 Adjustable Output Voltage (FB and ADJ)
        1. 7.3.8.1 OUT Voltage Equal to the Reference Voltage
        2. 7.3.8.2 OUT Voltage Higher Than Reference Voltage
        3. 7.3.8.3 Output Voltage Lower Than Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN < 4 V
      2. 7.4.2 Operation With EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application With Output Voltage Equal to the Reference Voltage
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input Capacitor
          2. 8.2.1.2.2 Output Capacitor
        3. 8.2.1.3 Application Curve
      2. 8.2.2 High-Side Switch Configuration
      3. 8.2.3 High Accuracy LDO
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation and Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resource
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

For the layout of the TPS7B4253-Q1 device, place the input and output capacitors close to the devices as shown in the Functional Block Diagram. To enhance the thermal performance, TI recommends surrounding the device with some vias.

Minimize equivalent series inductance (ESL) and ESR to maximize performance and ensure stability. Place every capacitor as close as possible to the device and on the same side of the PCB as the regulator.

Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI strongly discourages the use of vias and long traces for the path between the output capacitor and the OUT pins because vias can negatively impact system performance and even cause instability.

If possible, and to ensure the maximum performance specified in this data sheet, use the same layout pattern used for the TPS7B4253-Q1 evaluation board, TPS7B4253EVM, which is available at
www.ti.com/tool/TPS7B4253EVM.

10.2 Layout Example

TPS7B4253-Q1 layout_hsop_slvscp3.gif Figure 31. SO PowerPAD Package TPS7B4253-Q1 Layout Example
TPS7B4253-Q1 layout_htssop_slvscp3.gif Figure 32. HTSSOP Package TPS7B4253-Q1 Layout Example

10.3 Power Dissipation and Thermal Considerations

Use Equation 5 to calculate the device power dissipation.

Equation 5. TPS7B4253-Q1 eq_3_dissipation_slvsca0.gif

where

  • PD = continuous power dissipation
  • IO = output current
  • VI = input voltage
  • VO = output voltage
  • IQ = quiescent current

As IQ « IO, the term IQ × VI in Equation 5 can be ignored.

For a device under operation at a given ambient air temperature (TA), calculate the junction temperature (TJ) with Equation 6.

Equation 6. TPS7B4253-Q1 eq_4_tj_slvsca0.gif

where

  • θJA = junction-to-junction-ambient air thermal impedance

A rise in junction temperature because of power dissipation can be calculated with Equation 7.

Equation 7. TPS7B4253-Q1 eq_5_delta_tj_slvsca0.gif

For a given maximum junction temperature (TJmax), the maximum ambient air temperature (TAmax) at which the device can operate can be calculated with Equation 8.

Equation 8. TPS7B4253-Q1 q_6_max_ta_slvscp3.gif