SLVSFT8F February   2023  – December 2023 TPS7H1111-SEP , TPS7H1111-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply
      2. 8.3.2  Output Voltage Configuration
      3. 8.3.3  Output Voltage Configuration with a Voltage Source
      4. 8.3.4  Enable
      5. 8.3.5  Soft Start and Noise Reduction
      6. 8.3.6  Configurable Power Good
      7. 8.3.7  Current Limit
      8. 8.3.8  Stability
        1. 8.3.8.1 Output Capacitance
        2. 8.3.8.2 Compensation
      9. 8.3.9  Current Sharing
      10. 8.3.10 PSRR
      11. 8.3.11 Noise
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application 1: Set Turn-On Threshold with EN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Bias Supply
          2. 9.2.1.2.2 Output Voltage Configuration
          3. 9.2.1.2.3 Output Voltage Accuracy
          4. 9.2.1.2.4 Enable Threshold
          5. 9.2.1.2.5 Soft Start and Noise Reduction
          6. 9.2.1.2.6 Configurable Power Good
          7. 9.2.1.2.7 Current Limit
          8. 9.2.1.2.8 Output Capacitor and Ferrite Bead
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Application 2: Parallel Operation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Current Sharing
        3. 9.2.2.3 Application Results
    3. 9.3 Capacitors Tested
    4. 9.4 TID Effects
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HBL|14
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4 TID Effects

Most specifications listed in the Electrical Characteristics are tested using automated test equipment (ATE). These specifications are therefore easily tested both pre-irradiation and post-irradiation. Additionally, these specifications are generally part of the RLAT (radiation lot acceptance testing) flow. However, some specifications are difficult to measure on the ATE (such as due to high gain or sensitive to parasitics) and are therefore only measured during bench characterization. Typically these specifications are not measured post irradiation.

PSRR, noise, and stability are the key specifications that are not covered using the ATE and therefore not part of the traditional RLAT flow. In order to provide additional information for these key specifications, a one time characterization was performed on three EVMs. These three EVMs were biased and exposed at a high-dose-rate (HDR) to 100 krad(Si).

All PSRR, noise, and stability measurements showed good results under irradiation. The following generalities are made:

  • PSRR is measured marginally lower post TID in the 100 Hz to 1 kHz range. Unit 1 shows around 10 dB lower post TID; however, this is thought to be a setup related issue due to difficulty in measuring such high gain. In any event, the PSRR is still extremely high (>95 dB) within this range.
  • PSRR is measured marginally lower post TID under 100 Hz and above 1 kHz.
  • The noise is measured incrementally higher in the 10 Hz to 10 kHz range.
  • The noise is measured about the same below 10 Hz and above 100 kHz.
  • The RMS noise is calculated to be an average of 120 nVRMS higher post TID.
  • The average phase margin magnitude shift is around 7°. The phase margin remains high for all pre and post measurements.
  • The average gain margin magnitude shift is around 2 dB. This change is considered minimal and potentially within measurement error.

The complete data follows. Unless otherwise noted, the EVM conditions are VIN = 2.5 V, VOUT = 1.8 V, VBIAS = 5 V, COUT = 2x100 µF (see Table 9-4), CSS = 4.7 µF, RREF = 12.0 kΩ, RBIAS = 10 Ω, CBIAS = 4.7 µF, TA = 25°C, integrated noise reported with 10 Hz to 100 kHz bandwidth.

GUID-20230103-SS0I-SLJB-1BZQ-5RCH8GXSLD8K-low.svgFigure 9-6 PSRR with IOUT = 100 mA
GUID-20230103-SS0I-HM1J-S2T5-HCWHQZL49ZWH-low.svgFigure 9-8 Noise Spectral Density with
IOUT = 100 mA
GUID-20230103-SS0I-WQBP-1TKM-8MD3GCCRGQBG-low.svg
Pre-Irradiation: Phase Margin = 78°, Gain Margin = 24 dB
Post-Irradiation: Phase Margin = 82°, Gain Margin = 23 dB
Figure 9-10 Bode Plot: Unit 1 with IOUT = 100 mA
GUID-20230103-SS0I-RK7T-9FVX-Z04JCL6QT5SW-low.svg
Pre-Irradiation: Phase Margin = 81°, Gain Margin = 23 dB
Post-Irradiation: Phase Margin = 76°, Gain Margin = 26 dB
Figure 9-12 Bode Plot: Unit 2 with IOUT = 100 mA
GUID-20230103-SS0I-Q5PR-SHZJ-48X31RWP4WVG-low.svg
Pre-Irradiation: Phase Margin = 78°, Gain Margin = 24 dB
Post-Irradiation: Phase Margin = 81°, Gain Margin = 21 dB
Figure 9-14 Bode Plot: Unit 3 with IOUT = 100 mA
GUID-20230103-SS0I-0FBL-8M26-S7SGNMFCGXPX-low.svgFigure 9-7 PSRR with IOUT = 1 A
GUID-20230103-SS0I-CC6T-H7FV-JKMHLF6CLDHW-low.svgFigure 9-9 Noise Spectral Density with IOUT = 1 A
GUID-20230103-SS0I-GHKR-C5WZ-HNXSMDR2G2XT-low.svg
Pre-Irradiation: Phase Margin = 91°, Gain Margin = 18 dB
Post-Irradiation: Phase Margin = 100°, Gain Margin = 16 dB
Figure 9-11 Bode Plot: Unit 1 with IOUT = 1 A
GUID-20230103-SS0I-LZCB-4VRB-KJ6LDXRLXFNC-low.svg
Pre-Irradiation: Phase Margin = 96°, Gain Margin = 17 dB
Post-Irradiation: Phase Margin = 88°, Gain Margin = 19 dB
Figure 9-13 Bode Plot: Unit 2 with IOUT = 1 A
GUID-20230103-SS0I-N51F-FVXM-1HQJMXJMS1GF-low.svg
Pre-Irradiation: Phase Margin = 90°, Gain Margin = 18 dB
Post-Irradiation: Phase Margin = 101°, Gain Margin = 15 dB
Figure 9-15 Bode Plot: Unit 3 with IOUT = 1 A