SBVS414 November   2021 TPS7H1210-SEP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Enable Pin Operation
      3. 7.3.3 Programmable Soft-Start
      4. 7.3.4 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Operation
      2. 8.1.2 Capacitor Recommendations
      3. 8.1.3 Noise Reduction and Feed-Forward Capacitor Requirements
      4. 8.1.4 Power-Supply Rejection Ratio (PSRR)
      5. 8.1.5 Output Noise
      6. 8.1.6 Transient Response
      7. 8.1.7 Post DC-DC Converter Filtering
      8. 8.1.8 Power for Precision Analog
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don’ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Improve PSRR and Noise Performance
    2. 10.2 Layout Example
    3. 10.3 Thermal Performance
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Spice Models
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over |VIN| = 3 V, IOUT = 1 mA, CIN = 20 µF, COUT = 20 µF, CNR_SS = 0 nF, FB tied to OUT, EN tied to IN, over operating temperature range (TJ = –55°C to 125°C), unless otherwise noted.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES AND CURRENTS
VUVLO Undervoltage lockout threshold –2 V
|VDO| Dropout voltage VIN = –4.6 V, VOUT(set) = –5 V,
|VDO| = |VIN – VOUT(measured)|,
CIN = 30 µF		 IOUT = 0.5 A 224 325 mV
IOUT = 1 A 363 500
IOUT = 1 A, 
TJ = 25°C		 363 450
ICL Current limit VIN = –6 V, VOUT(SET) = –5 V,
VOUT(forced) = –4.5 V		 2.9 A
IQ Quiescent current VEN = 3 V, IOUT = 0 A 210 350 µA
IGND Ground current(2) VEN = 3 V, IOUT = 0.5 A 5 10 mA
|ISHDN| Shutdown current VEN = 0.4 V 1 3 µA
VEN = –0.4 V 1 3
IFB(LKG) Feedback leakage current(3) 14 75 nA
ACCURACY
VREF Reference voltage VFB = VREF –1.199 –1.182 –1.164 V
VACC Output voltage accuracy |VIN| = 3 V, 1 mA ≤ IOUT ≤ 1 A –2% ±1% 2%
|VIN| = 16.5 V, 1 mA ≤ IOUT ≤ 100 mA –2% ±1% 2%
|VIN| = 16.5 V, |VOUT| = 15.5 V,
IOUT = 1 A		 –2% ±1% 2%
ΔVOUT/ΔVIN Line regulation 3 V ≤ |VIN| ≤ 16.5 V –0.007% VOUT/V
ΔVOUT/ΔIOUT Load regulation 1 mA ≤ IOUT ≤ 1 A –0.5% VOUT/A
ENABLE
VEN(+HI) Enable turn-on (positive logic) 2 10 V
VEN(–HI) Enable turn-on (negative logic) VIN = –16.5 V VIN -2
VEN(+LO) Enable turn-off (positive logic) 0 0.4
VEN(–LO) Enable turn-off (negative logic) –0.4 0
|IEN| Enable current VIN = VEN = –3 V 0.48 1 µA
VIN = VEN = –16.5 V 0.51 1
VIN = –16.5 V, VEN = 10 V 0.5 1
TSD(enter) Thermal shutdown enter temperature 178 °C
TSD(exit) Thermal shutdown exit temperature 152
NOISE AND PSRR
PSRR Power-supply rejection ratio VIN = –6 V, VOUT = –5 V,
COUT = 50.11 µF, IOUT = 1 A,
CNR_SS = 100 nF(4)		 f = 100 Hz 61 dB
f = 100 kHz 61
f = 1 MHz 41
VN Output noise rms voltage (bandwidth from 10 Hz to 100 kHz) VIN = –3 V, VOUT(nom) = VREF, CIN = 11.1 µF, COUT = 50.11 µF, CNR_SS = 100 nF, IOUT = 1 A  13.7 µVRMS
(1) At operating conditions, VIN ≤ 0 V, VOUT(nom) ≤ VREF ≤ 0 V; at regulation, VIN ≤ VOUT(nom) – |VDO|; IOUT > 0 flows from OUT to IN.
(2) IGND = IIN – IOUT
(3) IFB > 0 flows into the device.
(4) CIN is removed as part of PSRR testing. During normal operation, follow the recommended operating condition of CIN ≥ 10 µF.