SLUSAN7C SEPTEMBER   2011  – April  2018 TPS84210

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application
      2.      Efficiency vs Output Current
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Package Specifications
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Switching Characteristics
    6. 6.6 Typical Characteristics (VIN = 5 V)
    7. 6.7 Typical Characteristics (VIN = 3.3 V)
  7. 7 Functional Block Diagram
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting The Output Voltage
  9. 9 Capacitor Recommendations For The TPS84210 Power Supply
    1. 9.1 Capacitor Technologies
      1. 9.1.1 Electrolytic, Polymer-Electrolytic Capacitors
      2. 9.1.2 Ceramic Capacitors
      3. 9.1.3 Tantalum, Polymer-Tantalum Capacitors
    2. 9.2 Input Capacitor
    3. 9.3 Output Capacitor
  10. 10Transient Response
  11. 11Application Schematics
  12. 12Power Good (PWRGD)
  13. 13Power-Up Characteristics
  14. 14Remote Sense
  15. 15Output On/Off Inhibit (INH)
  16. 16Slow Start (SS/TR)
  17. 17Overcurrent Protection
  18. 18Synchronization (CLK)
  19. 19Sequencing (SS/TR)
  20. 20Programmable Undervoltage Lockout (UVLO)
  21. 21Thermal Shutdown
  22. 22Layout Guidelines
  23. 23Layout Example
  24. 24EMI
  25. 25Device and Documentation Support
    1. 25.1 Receiving Notification of Documentation Updates
    2. 25.2 Community Resources
    3. 25.3 Trademarks
    4. 25.4 Electrostatic Discharge Caution
    5. 25.5 Glossary
  26. 26Mechanical, Packaging, and Orderable Information
    1. 26.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RKG|39
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Power Good (PWRGD)

The PWRGD pin is an open drain output. Once the voltage on the SENSE+ pin is between 93% and 105% of the set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pull-up resistor value is between 10 kΩ and 100 kΩ to a voltage source that is 6 V or less. The PWRGD pin is in a defined state once VIN is greater than 1.2 V, but with reduced current sinking capability. The PWRGD pin achieves full current sinking capability once the VIN pin is above 2.95V. Figure 21 shows the PWRGD waveform during power-up. The PWRGD pin is pulled low when the voltage on SENSE+ is lower than 91% or greater than 107% of the nominal set voltage. Also, the PWRGD pin is pulled low if the input UVLO or thermal shutdown is asserted, or if the INH pin is pulled low.