SLVSBK3A December   2012  – September 2015 TPS92690

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Current Regulators
      2. 7.3.2  Peak Current Mode Control
      3. 7.3.3  Switching Frequency and Synchronization
      4. 7.3.4  Current Sense and Current Limit
      5. 7.3.5  Average LED Current
      6. 7.3.6  Precision Reference (VREF)
      7. 7.3.7  Low-Level Analog Dimming
      8. 7.3.8  Soft-Start and Shutdown
      9. 7.3.9  VCC Regulator and Start-Up
      10. 7.3.10 Overvoltage Protection (OVP)
      11. 7.3.11 Input Undervoltage Lockout (UVLO)
      12. 7.3.12 PWM Dimming
      13. 7.3.13 Control Loop Compensation
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Inductor
      2. 8.1.2 LED Dynamic Resistance
      3. 8.1.3 Output Capacitor
      4. 8.1.4 Input Capacitor
      5. 8.1.5 MOSFET Selection
      6. 8.1.6 Recirculating Diode
    2. 8.2 Typical Applications
      1. 8.2.1 Basic Topology Schematics
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Operating Point
          2. 8.2.1.2.2  Switching Frequency
          3. 8.2.1.2.3  Average LED Current
          4. 8.2.1.2.4  Inductor Ripple Current
          5. 8.2.1.2.5  Output Capacitance
          6. 8.2.1.2.6  Peak Current Limit
          7. 8.2.1.2.7  Loop Compensation
          8. 8.2.1.2.8  Input Capacitance
          9. 8.2.1.2.9  NFET
          10. 8.2.1.2.10 Diode
          11. 8.2.1.2.11 Input UVLO
          12. 8.2.1.2.12 Output OVLO
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Simplified Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Operating Point
          2. 8.2.2.2.2  Switching Frequency
          3. 8.2.2.2.3  Average LED Current
          4. 8.2.2.2.4  Inductor Ripple Current
            1. 8.2.2.2.4.1 Minimum Inductor Value
            2. 8.2.2.2.4.2 Inductor Ripple Current
            3. 8.2.2.2.4.3 RMS Inductor Current
          5. 8.2.2.2.5  LED Ripple Current
            1. 8.2.2.2.5.1 Output Capacitor
            2. 8.2.2.2.5.2 Output Capacitor RMS Current
          6. 8.2.2.2.6  Peak Current Limit
          7. 8.2.2.2.7  Loop Compensation
            1. 8.2.2.2.7.1 Compensation Capacitor
            2. 8.2.2.2.7.2 RHP Zero
            3. 8.2.2.2.7.3 Output Capacitor Pole
          8. 8.2.2.2.8  Input Capacitance
          9. 8.2.2.2.9  NFET
            1. 8.2.2.2.9.1 Maximum Average NFET Current
            2. 8.2.2.2.9.2 RMS Transistor Current
          10. 8.2.2.2.10 Diode
            1. 8.2.2.2.10.1 Maximum Average Diode Current
          11. 8.2.2.2.11 Output OVLO
          12. 8.2.2.2.12 Input UVLO
          13. 8.2.2.2.13 Soft-Start
          14. 8.2.2.2.14 PWM Dimming Method
          15. 8.2.2.2.15 Analog Dimming Method
  9. 9 Power Supply Recommendations
    1. 9.1 Bench Supply Current Limit
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PWP Package
16-Pin HTSSOP With PowerPAD
Top View
TPS92690 pinout_pwp16_slvsbk3.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
AGND 7 GND Connect to PGND through DAP exposed thermal pad for proper ground return path.
COMP 6 I Connect ceramic capacitor to GND to set loop compensation.
CSP 11 I Connect to positive terminal of sense resistor in series with LED stack.
GATE 13 O Connect to main N-channel MOSFET gate of switching converter.
IADJ 10 I Connect resistor divider from VREF to set error amplifier reference voltage.
ILIM 8 I Connect resistor divider from VREF to set current limit threshold voltage at IS pin.
IS 14 I Connect to drain of main N-channel MOSFET or to source of MOSFET if sense resistor is used for improved accuracy.
nDIM 1 I Connect resistor divider from VIN to set UVLO threshold and hysteresis. Connect through diode or MOSFET to PWM dim concurrently.
OVP 2 I Connect resistor divider from output voltage to set OVP threshold and hysteresis.
PGND 12 GND Connect to AGND through the exposed thermal pad for proper ground return path.
RT 3 O Connect resistor to AGND to set base switching frequency.
SS/SD 5 I Connect capacitor to AGND to set soft-start delay. Pull pin below 75 mV for low-power shutdown.
SYNC 4 I Connect external PWM signal to set switching frequency. Must be higher than base frequency set at RT pin. Can also connect series resistor and capacitor to drain of main MOSFET and capacitor to AGND to implement zero-crossing detection for quasi-resonant topologies. In either case, a falling edge on SYNC triggers a new on-time at GATE. If tied to ground, internal oscillator is used.
VCC 15 O Bypass with 2.2-µF ceramic capacitor to provide bias supply for controller.
VIN 16 I Connect to input supply of converter. Bypass with 100-nF ceramic capacitor to AGND as close to the device as possible.
VREF 9 O Connect to the IADJ pin directly or through resistor divider. Bypass with 100-nF ceramic capacitor to AGND.
Thermal Pad GND