SLUSF35 November   2023 TPSM828510 , TPSM828511 , TPSM828512

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Schematic
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Precise Enable (EN)
      2. 8.3.2 MODE/SYNC
      3. 8.3.3 Undervoltage Lockout (UVLO)
      4. 8.3.4 Power-Good Output (PG)
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode Operation (PFM/PWM)
      3. 8.4.3 100% Duty-Cycle Operation
      4. 8.4.4 Current Limit and Short-Circuit Protection
      5. 8.4.5 Output Discharge
      6. 8.4.6 Soft Start / Tracking (SS/TR)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Output Voltage
        2. 9.2.2.2 Feedforward Capacitor
        3. 9.2.2.3 Input Capacitor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Voltage Tracking
      2. 9.3.2 Synchronizing to an External Clock
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
        1. 9.5.2.1 Thermal Consideration
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.6 Soft Start / Tracking (SS/TR)

The internal soft-start circuitry controls the output voltage slope during start-up. This control avoids excessive inrush current and makes sure a controlled output voltage rise time. This control also prevents unwanted voltage drops from high impedance power sources or batteries. When EN is set high to start operation, the device starts switching after a delay of about 200 μs, then the internal reference and hence VOUT rises with a slope controlled by an external capacitor connected to the SS/TR pin.

The SS/TR pin must not be connected to the SS/TR pin of other devices. TI recommends to keep CSS at less than or equal to 47 nF. Larger capacitance can not fully discharge to zero during start-up. In this case the device starts the output voltage ramp at a value above zero Volt, leading to a short time period of increased device inrush current.

Leaving the SS/TR pin not connected provides the fastest start-up ramp with 160 µs typically. A capacitor connected from SS/TR to GND is charged with 2.5 µA by an internal current source during soft start. After the voltage on SS/TR exceeds 0.6 V the internal reference voltage of 0.6 V takes over control. The capacitance required to set a certain ramp-time (tramp) therefore is:

Equation 4. C S S [ n F ] = 2.5 μ A × t r a m p [ m s ] 0.6 V

If the device is set to shutdown (EN = GND), undervoltage lockout, or thermal shutdown, an internal resistor pulls the SS/TR pin to GND to make sure a proper low level. Returning from those states causes a new start-up sequence.

A voltage of less than the internal reference voltage applied at SS/TR can be used as an external voltage reference. The following examples are potential applications for this feature:

  • Track an external reference controller voltage. The output voltage follows this voltage in both directions up and down in forced PWM mode. In PFM mode, the output voltage decreases based on the load current in combination with the output capacitor value.
  • Track another rail by connecting a voltage divider to the other rail and feed the junction point to SS/TR of this device as shown in Figure 9-28 and in Figure 9-29.
  • Voltage sequencing and synchronization of multiple supply rails. Connect for example the open drain PG outputs of other converters to SS/TR of this converter to hold off output voltage generation until the other rails are ready and stable.
  • Modulate the output voltage. The voltage level on the SS/TR pin can be changed dynamically during operation at any time after the device started switching. This can be used for example to implement dynamic core voltage scaling for MCUs/CPUs/SoCs.
Note: Apply external voltages above 0.6 V at SS/TR. This voltage is then ignored by the device and the internal reference voltage is used instead. The internal current source can pull the SS/TR pin with a pullup current of typical 2.5 μA above the 0.6-V level up to a level of approximately 1.5 V below VIN. This must be considered for the maximum voltage capability of the soft-start (SS) capacitor and for weak external voltage sources.