SLLS783C May   2009  – March 2016 TSB81BA3E

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Description Continued
  5. 5 Pin Configuration and Function
  6. 6 Electrical Specfications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Thermal Information
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics, Driver
    5. 6.5 Electrical Characteristics, Receiver
    6. 6.6 Electrical Characteristics, Device
    7. 6.7 Switching Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TTL Input Data
      2. 8.3.2 LVDS Output Data
    4. 8.4 Device Functional Modes
      1. 8.4.1 Input Clock Edge
      2. 8.4.2 Low Power Mode
      3. 8.4.3 1394b Port Interface Considerations
    5. 8.5 Programming
      1. 8.5.1 Power-Class
    6. 8.6 Register Maps
      1. 8.6.1 Internal Register Configuration
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Port Termination for a 1394 Bilingual Port
        2. 9.2.2.2 PHY-LINK Interface
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Stackup
      2. 11.1.2 Digital and Analog Partitioning
      3. 11.1.3 Image Planes
      4. 11.1.4 Parts Placement
      5. 11.1.5 Decoupling Capacitors
      6. 11.1.6 3W Rule for SCLK
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Designing With PowerPAD Devices (PFP Package Only)

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Electrical Specfications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD Supply voltage range(2) –0.3 4 V
VI Input voltage range(2) –0.5 VDD + 0.5 V
VO Output voltage range at any output –0.5 VDD + 0.5 V
Continuous total power dissipation See Dissipation Ratings Table
TA Operating free-air temperature TSB81BA3E 0 70 °C
TSB81BA3EI –40 85
Tstg Storage temperature range 65 150 °C
Lead temperature 1.6 mm (1/16 in) from case for 10 s 260 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground.

6.2 Thermal Information

THERMAL METRIC(1) TSB81BA3E UNIT
PFP (HTQFP) ZJA (NFBGA)
80 PINS 167 PINS
RθJA Junction-to-ambient thermal resistance Low K JEDEC Test Board, 1s (single signal layer), no air flow 27.2 46.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance High K JEDEC Test Board 2s2p (double signal layer, double buried power plane) 8.9 23.5 °C/W
RθJB Junction-to-board thermal resistance Cu Cold Plate Measurement Process 11.1 27.8 °C/W
ψJT Junction-to-top characterization parameter EIA/JESD 51-8 0.3 0.45 °C/W
ψJB Junction-to-board characterization parameter EIA/JESD 51-2 11.0 27.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance EIA/JESD 51-6 0.3 N/A °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.3 Recommended Operating Conditions

MIN TYP(1) MAX UNIT
3.3 VDD Supply voltage Source power node 3.0 3.3 3.6 V
Nonsource power node 3.0(2) 3.3 3.6
Core VDD Supply voltage 1.85 1.95 2.05 V
VIH High-level input voltage LREQ, CTL0, CTL1, D0-D7, LCLK 2.6 V
LKON/DS2, PC0, PC1, PC2, PD, BMODE 0.7 × VDD
RESETz 0.6 × VDD
VIL Low-level input voltage LREQ, CTL0, CTL1, D0-D7, LCLK 1.2 V
LKON/DS2, PC0, PC1, PC2, PD, BMODE 0.2 × VDD
RESETz 0.3 × VDD
VOD 1394b Differential output voltage 700 mV
VCM 1394b Common-mode output voltage 1.5 V
IDD Supply current in low power/suspend(4) VD D = 3.3 V 4 mA
VD D = 3 V 3 mA
IOL/OH Output current CTL0, CTL1, D0-D7, CNA, LKON/DS2, PINT, and PCLK –4 4 mA
IO Output current TPBIAS outputs –5.6 1.3 mA
TA Operating ambient temperature range TSB81BA3E 0 70 °C
TJ Junction temperature(5) TSB81BA3E 0 105 °C
VID 1394b Differential input voltage Cable inputs, during data reception 200 800 mV
VID 1394a Differential input voltage Cable inputs, during data reception 118 260 mV
Cable inputs, during arbitration 168 265
VIC 1394a Common-mode input voltage TPB cable inputs, source power node 0.4706 2.515 V
TPB cable inputs, nonsource power node 0.4706 2.015(2)
tpu Power-up reset time RESETz input 2(3) ms
Receive input jitter TPA, TPB cable inputs, S100 operation ±1.08 ns
TPA, TPB cable inputs, S200 operation ±0.5
TPA, TPB cable inputs, S400 operation ±0.315
Receive input skew Between TPA and TPB cable inputs, S100 operation ±0.8 ns
Between TPA and TPB cable inputs, S200 operation ±0.55
Between TPA and TPB cable inputs, S400 operation ±0.5
(1) All typical values are at VDD = 3.3 V and TA = 25°C.
(2) For a node that does not source power, see Section 4.2.2.2 in IEEE 1394a-2000.
(3) Time after valid clock received at PHY XI input terminal.
(4) The low power/suspend mode assumes that the device is not receiving packets and it is toning.
(5) The junction temperature reflects simulated conditions. The customer is responsible for verifying junction temperature.

6.4 Electrical Characteristics, Driver

over recommended ranges of operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOD Differential output voltage 56 Ω, See Figure 1 172 265 mV
IDIFF Driver difference current, TPA+, TPA–, TPB+, TPB– Drivers enabled, speed signaling off –1.05(1) 1.05(1) mA
ISP200 Common-mode speed signaling current, TPB+, TPB– S200 speed signaling enabled –4.84(2) –2.53(2) mA
ISP400 Common-mode speed signaling current, TPB+, TPB– S400 speed signaling enabled –12.4(2) –8.1(2) mA
VOFF Off-state differential voltage Drivers disabled, See Figure 1 20 mV
(1) Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to TPB+ and TPB– algebraic sum of driver currents.
(2) Limits defined as absolute limit of each of TPB+ and TPB– driver currents.

6.5 Electrical Characteristics, Receiver

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ZID Differential impedance Drivers disabled 4 7 kΩ
4 pF
ZIC Common-mode impedance Drivers disabled 20 kΩ
24 pF
VTH-R Receiver input threshold voltage Drivers disabled –30 30 mV
VTH-CB Cable bias detect threshold, TPBx cable inputs Drivers disabled 0.6 1 V
VTH+ Positive arbitration comparator threshold voltage Drivers disabled 89 168 mV
VTH– Negative arbitration comparator threshold voltage Drivers disabled –168 –89 mV
VTH-SP200 Speed signal threshold TPBIAS-TPA common-mode voltage, drivers disabled 49 131 mV
VTH-SP400 Speed signal threshold 314 396 mV

6.6 Electrical Characteristics, Device

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDD Supply current 3.3 VDD  (2) 120 150 mA
Core VDD 79
VTH Power status threshold, CPS input(1) 400-kΩ resistor(1) 4.7 7.5 V
VOH High-level output voltage, CTL0, CTL1, D0-D7, PCLK, LKON/DS2 outputs VDD = 3 to 3.6 V,
IOH = 4 mA		 2.8 V
VOL Low-level output voltage, CTL0, CTL1, D0-D7, PCLK, LKON/DS2 outputs IOL = 4 mA 0.4 V
IBH+ Positive peak bus holder current, D0-D7, CTL0-CTL1, LREQ VDD = 3.6 V,
VI = 0 V to VDD 		0.05 1 mA
IBH– Negative peak bus holder current, D0-D7, CTL0-CTL1, LREQ VDD = 3.6 V,
VI = 0 V to VDD 		–1.0 –0.05 mA
IOZ Off-state output current, CTL0, CTL1, D0-D7, LKON/DS2 I/Os VO = VDD or 0 V TSB81BA3E ±5 μA
TSB81BA3EI ±20
IIRST Pullup current, RESET input VI = 1.5 V or 0 V –90 –20 μA
VO TPBIAS output voltage At rated IO current 1.665 2.015 V
(1) Measured at cable-power side of resistor.
(2) Repeat max packet (one port receiving maximum size isochronous packet–8192 bytes, sent on every isochronous interval, S800, data value of 0xCCCCCCCCh; two ports repeating; all ports with beta-mode connection), VDD3.3 = 3.3 V, V DDCORE = 1.95 V, TA = 25°C.

6.7 Switching Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr TP differential rise time, transmit 10% to 90%, At 1394 connector 0.5 1.2 ns
tf TP differential fall time, transmit 90% to 10%, At 1394 connector 0.5 1.2 ns
tsu Setup time,
CTL0, CTL1, D1-D7, LREQ to PCLK		 1394a-2000 50% to 50%, See Figure 2 2.5 ns
th Hold time,
CTL0, CTL1, D1-D7, LREQ after PCLK		 1394a-2000 50% to 50%, See Figure 2 0 ns
tsu Setup time,
CTL0, CTL1, D1-D7, LREQ to LCLK_PMC		 1394b 50% to 50%, See Figure 2 2.5 ns
th Hold time,
CTL0, CTL1, D1-D7, LREQ after LCLK_PMC		 1394b 50% to 50%, See Figure 2 0 ns
td Delay time,
PCLK to CTL0, CTL1, D1-D7, PINT		 1394a-2000 and 1394b 50% to 50%, See Figure 3 0.5 7 ns