SLVSHH6A August   2023  – October 2023 TSM24A

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings - JEDEC Specifications
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  8. 7Application and Implementation
    1. 7.1 Application Information
  9. 8Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

At TA = 25°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 100 nA 24 V
ILEAK Leakage current at VRWM VIO = 24 V, I/O to GND 25 75 nA
VBR Breakdown voltage, I/O to GND (1) IIO = 10 mA 26 29 V
VFWD Forward Voltage, GND to I/O (1) IIO = 10 mA 0.7 V
VCLAMP Surge clamping voltage, tp = 8/20 µs (2) IPP = 60 A, I/O to GND 38 V
VCLAMP Surge clamping voltage, tp = 8/20 µs (2) IPP = 60 A, GND to I/O 7 V
CLINE Line capacitance, IO to GND VIO = 0 V, f = 1 MHz 54 pF
(1) VBR is defined as the voltage when 10 mA is applied in the positive-going direction.
(2) Device stressed with 8/20 µs exponential decay waveform according to IEC 61000-4-5