4 Revision History
Changes from Revision A (February 2021) to Revision B (December 2021)
- Updated the numbering format for tables, figures, and
cross-references throughout the documentGo
- Removed 1M feedback resistor requirement for crystal on pages
4, 11, 12, and 31Go
- Corrected the default register setting for the Register offset
9h
Go
Changes from Revision * (July 2015) to Revision A (February 2021)
- Added AEQ-Q100 Device Temperature Grade 3 bullet to feature
listGo
- From: SMBus slave address bits 2
and 3 are always 1 for TUSB4020BI-Q1 To: SMBus
slave address bit 3 is always 1 for
TUSB4020BI-Q1Go