SLUS352C January   1997  – December 2015 UC1846 , UC2846 , UC3846 , UC3847

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Sense Amplifier
      2. 7.3.2 Oscillator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Current Limit
      2. 7.4.2 Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Design Switching Frequency
        2. 8.2.2.2 Error Amplifier Output Configuration
        3. 8.2.2.3 Parallel Operation Configuration
        4. 8.2.2.4 Design Pulse by Pulse Current Limit Threshold
        5. 8.2.2.5 Soft-Start and Shutdown, Restart Function Design
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|16
  • N|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

  • Place a low ESR and ESL decoupling capacitor CREF in the 1-µF to 2.2-µF range, preferably ceramic, from VREF pin to GND.
  • The EA+ is a non-inverting input, the EA– is an inverting input and the COMP is the output of the error amplifier. Place resistor and capacitor series network between EA+ pin and COMP pin, and reduce the trace of resistor and capacitor series network as much as possible.
  • Place a low ESR and ESL capacitor CT, preferably ceramic, from CT pin to GND, and place CT close to UCx846/7 as much as possible.
  • Place a resistor RT from RT pin to GND, and place RT close to UCx846/7 as much as possible.

10.2 Layout Example

UC1846 UC1847 UC2846 UC2847 UC3846 UC3847 layout_lus352.gif Figure 12. UCx84x Layout Example