Table 8. System Design Specifications

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the UCC256304 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.

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In most cases, these actions are available:

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• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
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Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 LLC Power Stage Requirements

Start the design by deciding the LLC power stage component values. The LLC power stage design procedure outlined here follows the one given in the TI application note “Designing an LLC Resonant Half-Bridge Power Converters”. The application note contains a full explanation of the origin of each of the equations used. The equations given below are based on the First Harmonic Approximation (FHA) method commonly used to analyze the LLC topology. This method gives a good starting point for any design, but a final design requires an iterative approach combining the FHA results, circuit simulation, and hardware testing. An alternative design approach is given in TI application note SLUA733, LLC Design for UCC29950.

8.2.2.3 LLC Gain Range

First, determine the transformer turns ratio by the nominal input and output voltages.

Equation 10.

Then determine the LLC gain range M_g(min) and M_g(max). Assume there is a 0.5-V drop in the rectifier diodes (V_f) and a further 0.5-V drop due to other losses (V_loss).

Equation 11.

Equation 12.

8.2.2.4 Select L_n and Q_e

L_n is the ratio between the magnetizing inductance and the resonant inductance.

Equation 13.

Q_e is the quality factor of the resonant tank.

Equation 14.

In this equation, R_e is the equivalent load resistance.

Selecting L_n and Q_e values should result in an LLC gain curve, as shown below, that intersects with M_g(min) and M_g(max) traces. The peak gain of the resulting curve should be larger than M_g(max). Details of how to select L_n and Q_e are not discussed here. They are available in the Application Note, UCC25630x Practical Design Guidelines and UCC256304 Design Calculator.

In this case, the selected L_n and Q_e values are:

Equation 15.

Equation 16.

8.2.2.5 Determine Equivalent Load Resistance

Determine the equivalent load resistance by Equation 17.

Equation 17.

8.2.2.6 Determine Component Parameters for LLC Resonant Circuit

Before determining the resonant tank component parameters, a nominal switching frequency (resonant frequency) should be selected. In this design, 100 kHz is selected as the resonant frequency.

Equation 18.

The resonant tank parameters can be calculated as the following:

Equation 19.

Equation 20.

Equation 21.

After the preliminary parameters are selected, find the closest actual component value that is available, re-check the gain curve with the selected parameters, and then run time domain simulation to verify the circuit operation.

The following resonant tank parameters are:

Equation 22.

Equation 23.

Equation 24.

Based on the final resonant tank parameters, the resonant frequency can be calculated:

Equation 25.

Based on the new LLC gain curve, the normalized switching frequency at maximum and minimum gain are given by:

Equation 26.

Equation 27.

The maximum and minimum switching frequencies are:

Equation 28.

Equation 29.

8.2.2.7 LLC Primary-Side Currents

The primary-side currents are calculated for component selection purpose. The currents are calculated based on a 110% overload condition.

The primary side RMS load current is given by:

Equation 30.

The RMS magnetizing current at minimum switching frequency is given by:

Equation 31.

The total current in resonant tank is given by:

Equation 32.

8.2.2.8 LLC Secondary-Side Currents

The total secondary side RMS load current is the current referred from the primary side current (I_oe) to the secondary side.

Equation 33.

In this design, the transformer’s secondary side has a center-tapped configuration. The current of each secondary transformer winding is calculated by:

Equation 34.

The corresponding half-wave average current is:

Equation 35.

8.2.2.9 LLC Transformer

A bias winding is needed in order to utilize the HV self start up function. It is recommended to design the bias winding so that the VCC voltage is greater than 13 V.

The transformer can be built or purchased according to these specifications:

• Turns ratio: Primary : Secondary : Bias = 32 : 2 : 3
• Primary terminal voltage: 450Vac
• Primary magnetizing inductance: L_M = 830 µH
• Primary side winding rated current: I_r = 1.009 A
• Secondary terminal voltage: 36V_ac
• Secondary winding rated current: I_ws = 8.639 A
• Minimum switching frequency: 50.3 kHz
• Maximum switching frequency: 111.3 kHz
• Insulation between primary and secondary sides: IEC60950 reinforced insulation

The minimum operating frequency during normal operation is that calculated above but during shutdown the LLC can operate at right above ZCS boundary condition, which is a lower frequency. The magnetic components in the resonant circuit, the transformer and resonant inductor, should be rated to operate at this lower frequency.

8.2.2.10 LLC Resonant Inductor

The AC voltage across the resonant inductor is given by its impedance times the current:

Equation 36.

The inductor can be built or purchased according to the following specifications:

• Inductance: L_r = 61.5 µH
• Rated current: I_r = 1.009 A
• Terminal AC voltage:
• Frequency range: 50.3 kHz to 111.3 kHz

The minimum operating frequency during normal operation is that calculated above but during shutdown the LLC can operate at right above ZCS boundary condition, which is a lower frequency. The magnetic components in the resonant circuit, the transformer and resonant inductor, should be rated to operate at this lower frequency.

8.2.2.11 LLC Resonant Capacitor

This capacitor carries the full-primary current at a high frequency. A low dissipation factor part is needed to prevent overheating in the part.

The AC voltage across the resonant capacitor is given by its impedance times the current.

Equation 37.

Equation 38.

Peak voltage:

Equation 39.

Valley voltage:

Equation 40.

Rated current:

Equation 41.

8.2.2.12 LLC Primary-Side MOSFETs

Each MOSFET sees the input voltage as its maximum applied voltage. Choose the MOSFET voltage rating to be 1.5 times of the maximum bulk voltage:

Equation 42.

Choose the MOSFET current rating to be 1.1 times of the maximum primary side RMS current:

Equation 43.

8.2.2.13 Design Considerations for Adaptive Dead-Time

After the resonant tank is designed and the primary side MOSFET is selected, the ZVS operation of the converter needs to be double checked. ZVS can only be achieved when there is enough current left in the resonant inductor at the gate turn off edge to discharge the switch node. UCC256304 implements adaptive dead-time based on the slewing of the switch node. The slew detection circuit has a detection range of 1V/ns to 50 V/ns.

To check the ZVS operation, a series of time domain simulations are conducted, and the resonant current at the gate turn off edges are captured. An example plot is shown below:

Figure 54. Adaptive Dead-Time

The figure above assumes the maximum switching frequency occurs at 5% load, and system starts to burst at 5% load.

From this plot, the minimum resonant current left in the tank is I_min = 0.8 A in the interested operation range. In order to calculate the slew rate, the primary side switch node parasitic capacitance must be known. This value can be estimated from the MOSFET datasheet. In this case, C_switchnode = 400 pF. The minimum slew rate is given by:

Equation 44.

This is larger than 1 V/ns minimum detectable slew rate.

8.2.2.14 LLC Rectifier Diodes

The voltage rating of the output diodes is given by:

Equation 45.

The current rating of the output diodes is given by:

Equation 46.

8.2.2.15 LLC Output Capacitors

The LLC converter topology does not require an output filter although a small second stage filter inductor may be useful in reducing peak-to-peak output noise. Assuming that the output capacitors carry the rectifier’s full wave output current then the capacitor ripple current rating is:

Equation 47.

Use 20 V rating for 12-V output voltage:

Equation 48.

The capacitor’s RMS current rating is:

Equation 49.

Solid Aluminum capacitors with conductive polymer technology have high ripple-current ratings and are a good choice here. The ripple-current rating for a single capacitor may not be sufficient so multiple capacitors are often connected in parallel.

The ripple voltage at the output of the LLC stage is a function of the amount of AC current that flows in the capacitors. To estimate this voltage, assume that all the current, including the DC current in the load, flows in the filter capacitors.

Equation 50.

The capacitor specifications are:

• Voltage Rating: 20 V
• Ripple Current Rating: 4.84 A
• ESR: < 19 mΩ

8.2.2.16 HV Pin Series Resistors

Multiple resistors are connected in series with HV pin to limit the power dissipation of the UCC256304 device. The recommended series resistor with HV pin is 5 kΩ.

8.2.2.17 BLK Pin Voltage Divider

BLK pin senses the LLC input voltage and determines when to turn on and off the LLC converter. Different versions of UCC256304 have different BLK thresholds.

Choose bulk startup voltage at 340 V, then the BLK resistor divider ratio can be calculated as below:

Equation 51.

The desired power consumption of the BLK pin resistor divider is P_BLKsns = 10 mW. The BLK sense resistor total value is given by:

Equation 52.

The lower BLK divider resistor value is given by:

Equation 53.

The higher BLK divider resistor value is given by:

Equation 54.

The actual bulk voltage thresholds can be calculated:

Equation 55.

Equation 56.

Equation 57.

Equation 58.

8.2.2.18 BW Pin Voltage Divider

BW pin senses the output voltage through the bias winding and protects the power stage from over voltage. The nominal output voltage is 12 V. The bias winding has 3 turns, and the secondary side winding has 2 turns. So the nominal voltage of the bias winding is given by:

Equation 59.

The desired OVP threshold in this design is 115% of the nominal value. The OVP threshold level in UCC256304 device is 4 V, so the nominal BW pin voltage is given by:

Equation 60.

Choose the lower resistor of the BW resistor divider to be 10 kΩ.

Equation 61.

The upper resistor can be calculated by:

Equation 62.

8.2.2.19 ISNS Pin Differentiator

ISNS pin sets the over current protection level. OCP1 is peak current protection level; OCP2 and OCP3 are average current protection levels. The threshold voltages are 0.6 V, 0.8 V, and 4 V, respectively.

Set OCP3 level at 150% of full load. Thus, the sensed average input current level at full load is given by:

Equation 63.

The current sense ratio can then be calculated:

Equation 64.

Select a current sense capacitor first, since there are less high voltage capacitor choices than resistors:

Equation 65.

Then calculate the required ISNS resistor value:

Equation 66.

After the current sense ratio is determined, the peak ISNS pin voltage at full load can be calculated:

Equation 67.

The peak resonant current at OCP1 level is given by:

Equation 68.

The peak secondary-side current at OCP1 level is given by:

Equation 69.

8.2.2.20 VCR Pin Capacitor Divider

The capacitor divider on the VCR pin sets two parameters: (1) the divider ratio of the resonant capacitor voltage; (2) the amount of frequency compensation to be added. The first criteria the capacitor divider needs to meet is that under over load condition, the peak-to-peak voltage on VCR pin is with in 6 V.

As derived earlier, the following relationship between VCOMP voltage, ΔVCR, switching period, input average current, and the VCR capacitor divider is shown in Equation 70

Equation 70.

In this equation, C₁ is the upper capacitor on the capacitor divider; C₂ is the lower capacitor on the capacitor divider. VCOMP is contributed by two parts – the divided resonant capacitor voltage, and the voltage generated by the VCR pin internal current sources. Define the contribution of the internal current source to be K_VCRRamp.

Equation 71.

Select C₁ and C₂ so that K_VCRRamp is within 0.1 ~ 0.6 range, and at over load condition, VCOMP is less than 6 V. In this example C₁ = 150 pF and C₂ = 15 nF is select.

8.2.2.21 Burst Mode Programming

The burst mode programming interface enables user to program a burst mode threshold voltage (VLL) which adaptively changes with input voltage. This way, consistent burst threshold can be achieved across V_IN range, thus making the efficiency curve more consistent across V_IN range.

The following relationship exists between VLL voltage and BLK pin voltage:

Equation 72.

In this equation, VLL is the burst mode threshold voltage; VBLK is BLK pin voltage; two parameters a and b can be programmed by two external resistors.

After soft start is done, the sensed BLK pin voltage is applied to LL/SS pin from inside the IC through a buffer. As shown in the figure below, this creates a difference between the current flowing through the programming resistor R_LLUpper and R_LLLower. The difference between the current flows into the LL/SS pin, mirrored and then applied to a 250-kΩ resistor R_LL. The voltage on R_LL is used as VLL.

Figure 55. Burst Mode Programming

The relationship between VLL and VBLK can then be derived:

Equation 73.

Equation 73 rearranged produces Equation 74

Equation 74.

To determine R_LLUpper and R_LLLower, two sets of (VLL, VBLK) values are required. VBLK can be measured directly from BLK pin. VLL level can be measured by inserting a 10-kΩ resistor between the feedback optocoupler emitter and ground. Assume the voltage measured on the 10-kΩ resistor is V_10k. Then VLL voltage can be calculated as:

Equation 75.

Remove the R_LLUpper. In this way, the VLL voltage is at its minimal value 0.7 V, which is determined by the internal circuit design. Then adjust the load current to the desired burst mode threshold load level, and make sure the power stage does not burst in this condition. For example, 10% load is the desired burst mode threshold level. With 10 A as the full-load condition, set the load current to 1 A. After the load current is set, change the input voltage to two different voltages and record two different readings (V10k, VBLK). Then based on Equation 74 and Equation 75, R_LLUpper and R_LLLower can be solved.

In this example select the lower resistor to be 402 kΩ and the upper resistor to be 732 kΩ.

8.2.2.22 Soft-Start Capacitor

The soft-start capacitor sets the speed of the soft-start ramp. The soft start time varies with load condition. At full load or over load condition, the soft start time is the longest. It is not easy to calculate the exact soft start time value. However, it can be estimated that under full load condition, the longest possible soft start time is given by:

Equation 76.

Using a 150-nF soft-start capacitor, gives the longest possible soft-start time as 42 ms according to Equation 76.