SLUSFC7 july   2023 UCC27444

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Supply Current
      2. 7.3.2 Input Stage
      3. 7.3.3 Enable Function
      4. 7.3.4 Output Stage
      5. 7.3.5 Low Propagation Delays and Tightly Matched Outputs
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD and Power On Reset
        2. 8.2.2.2 Drive Current and Power Dissipation
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Unless otherwise noted, VDD = 4.5 V to 18 V, TA = TJ = –40°C to 125°C, 1-µF capacitor from VDD to GND, no load on the output. Typical condition specifications are at 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS CURRENTS
IVDD VDD static supply current VINx = 3.3 V, ENx = VDD 150 380 uA
IVDD VDD static supply current VINx = 0 V, ENx = VDD

107

180

uA
IVDDO VDD operating current CLOAD = 1.8 nF, fSW = 1000 kHz, ENx = VDD, VINx = 0 V – 3.3 V PWM

39

45

 mA
IDIS VDD disable current VINx = 3.3 V, ENx = 0 V

450

570

uA
POWER ON RESET (POR)
VVDD_ON VDD POR rising threshold 2.1

3.0

 4.0 V
VVDD_OFF VDD POR falling threshold 1.8 2.7 3.5 V
VVDD_HYS VDD POR hysteresis 0.3 V
INPUT (INA, INB)
VINx_H Input signal high threshold Output High, ENx = HIGH 1.6

2.2

 2.5 V
VINx_L Input signal low threshold Output Low, ENx = HIGH 0.8 1.2 1.5 V
VINx_HYS Input signal hysteresis

1

 V
ENABLE (ENA, ENB)
VENx_H Enable signal high threshold Output High, INx = HIGH 1.7 2.3 2.7 V
VENx_L Enable signal low threshold Output Low, INx = HIGH 1.1 1.8 2.2 V
VENx_HYS Enable signal hysteresis 0.7 V
RENx EN pin pullup resistance ENx = 0 V 100 kΩ
OUTPUTS (OUTA, OUTB)
ISRC(1) Peak output source current VDD = 14 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz 4 A
ISNK(1) Peak output sink current VDD = 14 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz –4 A
ROH(2) Pullup resistance IOUT = –10 mA

See Section 7.3.4.

1.2

 2.5 Ω
ROL Pulldown resistance IOUT = 10 mA 0.7 1.2 Ω
(1) Parameter not tested in production.
(2) Output pullup resistance in this table is a DC measurement that measures resistance of PMOS structure only (not N-channel structure).