SLUS161E April 1999 – August 2016 UCC2813-0 , UCC2813-1 , UCC2813-2 , UCC2813-3 , UCC2813-4 , UCC2813-5 , UCC3813-0 , UCC3813-1 , UCC3813-2 , UCC3813-3 , UCC3813-4 , UCC3813-5
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The UCCx813-x controllers are peak-current-mode (PCM) pulse-width modulators (PWM). These controllers have an onboard amplifier and can be used in isolated and nonisolated power supply design. There is an onboard totem-pole gate driver capable of delivering up to ±1 A of peak current. These controllers are capable of operating at switching frequencies up to 1 MHz.
Figure 33 illustrates a typical circuit diagram for an AC-DC converter using the UCC2813-0 in a peak-current-mode-controlled flyback application.
Use the parameters in Table 2 to review the design of a 12-V, 48-W offline flyback converter using the UCC2813-0 PWM controller.
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT CHARACTERSTICS | ||||||
V_{IN} | Input voltage (RMS) | 85 | 265 | V | ||
f_{LINE} | Line frequency | 47 | 63 | Hz | ||
OUTPUT CHARACTRSTICS | ||||||
V_{OUT} | Output voltage | 11.75 | 12 | 12.25 | V | |
V_{ripple} | Output ripple voltage | 120 | mV_{PP} | |||
I_{OUT} | Output current | 4 | 4.33 | A | ||
V_{tran} | Output transient | Output voltage measured under 0-A to 4-A load step | 11.75 | 12.25 | V | |
SYSTEM CHARACTRSTICS | ||||||
η | Max load efficiency | 85% |
The design starts with selecting an appropriate bulk capacitor.
The primary-side bulk capacitor is selected based on the input power level and on the desired minimum bulk voltage level. The bulk capacitor value can be calculated by Equation 5.
where
Based on this equation, to achieve 75-V minimum bulk voltage, assuming 85% converter efficiency and 47-Hz minimum line frequency, the bulk capacitor must be larger than 127 µF. 180 µF was chosen in the design, considering the typical tolerance of bulk capacitors.
The transformer design starts with selecting a suitable switching frequency. Generally the switching frequency selection is based on a tradeoff between the converter size and efficiency, based on the simple Flyback topology. Normally, higher switching frequency results in smaller transformer size. However, the switching loss is increased and hurts the efficiency. Sometimes, the switching frequency is selected to avoid certain communication bands to prevent noise interference with the communication. The frequency selection is beyond the scope of this data sheet.
The switching frequency is targeted for 110 kHz, to minimize the transformer size. At the same time, because EMI regulations start to limit conducted noise at 150 kHz, choosing 110-kHz switching frequency can help to reduce the EMI filter size.
The transformer turns ratio can be selected based on the desired MOSFET voltage rating and diode voltage rating. Because maximum input voltage is 265 V AC, the peak bulk voltage can be calculated by Equation 6.
To minimize the cost of the system, a popular 650-V MOSFET is selected. Considering the design margin and extra voltage ringing on the MOSFET drain, the reflected output voltage must be less than 120 V. The transformer turns ratio can be selected by Equation 7.
The transformer inductance selection is based on the continuous conduction mode (CCM) condition. Higher inductance would allow the converter to stay in CCM longer. However, it tends to increase the transformer size. Normally, the transformer magnetizing inductance is selected so that the converter enters CCM operation at about 50% load at minimum line voltage. This would be a tradeoff between the transformer size and the efficiency. In this particular design, due to the higher output current, it is desired to keep the converter deeper in CCM and minimize the conduction loss and output ripple. The converter enters CCM operation at about 10% load at minimum bulk voltage.
The inductor can be calculated as Equation 8.
In this equation, the switching frequency is 110 kHz. Therefore, the transformer inductance must be about 1.7 mH. 1.5 mH is chosen as the magnetizing inductance value.
The auxiliary winding provides the bias power for UCC2813-0 normal operation. The auxiliary winding voltage is the output voltage reflected to the primary side. It is desired to have higher reflected voltage so that the IC can quickly get energy from the transformer and make start-up under heavy load easier. However, higher reflected voltage makes the IC consume more power. Therefore, a tradeoff is required.
In this design, the auxiliary winding voltage is selected to be the same as the output voltage so that it is above the UVLO level but keeps the IC and driving loss low. Therefore, the auxiliary winding to the output winding turns ratio is selected by Equation 9.
Based on calculated primary inductance value and the switching frequency, the current stress of the MOSFET and diode can be calculated.
The peak current of the MOSFET is calculated by Equation 10.
The MOSFET peak current is 1.425 A.
The RMS current of the MOSFET can be calculated as Equation 11.
where
The MOSFET RMS current is 0.75 A. With less than 0.9-Ω on-resistance, IRFB9N65A is selected as the primary-side MOSFET.
The diode peak current is the reflected MOSFET peak current on the secondary side.
The diode voltage stress is the output voltage plus the reflected input voltage. The voltage stress on the diode can be calculated by Equation 14.
Considering the ringing voltage spikes and voltage derating, the diode voltage rating must be higher than 50 V.
The diode average current is the output current (4 A), so 48CTQ060-1, with 60-V rating and 40-A average current capability, is selected.
The output capacitor is selected based on the output voltage ripple requirement. In this design, 0.1% voltage ripple is assumed. Based on the 0.1% ripple requirement, the capacitor value can be selected based on Equation 15.
Considering the tolerance and temperature effect, together the ripple current rating of the capacitors, 3 parallel 680-µF capacitors are selected for the output.
After the basic power stage is designed, the surrounding controller components can be selected.
The current sensing network consists of R_{CS}, R_{CSF}, C_{CSF}, and optional R_{P}. Typically, the direct current sense signal contains a large-amplitude leading-edge spike associated with the turn-on of the main power MOSFET, reverse recovery of the output rectifier, and other factors including charging and discharging of parasitic capacitances. Therefore, C_{CSF} and R_{CSF} form a low-pass filter that provides additional immunity beyond the internal blanking time to suppress the leading edge spike. For this converter, C_{CSF} is chosen to be 270 pF to provide enough filtering.
Without R_{P}, R_{CS} sets the maximum peak current in the transformer primary based on the maximum amplitude of CS pin, 1 V. To achieve 1.425-A primary side peak current, a 0.75-Ω resistor is chosen for R_{CS}.
The high current-sense threshold helps to provide better noise immunity but the current-sense loss is increased. The current-sense loss can be minimized by injecting an offset voltage into the current-sense signal. R_{P} and R_{CSF} form a resistor-divider network from the current-sense signal to the device’s reference voltage to offset the current-sense voltage. This technique still achieves current-mode control with cycle-by-cycle overcurrent protection. To calculate required offset value (Voffset), use Equation 16.
R_{G} is the gate driver resistor for the power switch, Q_{A}. The selection of this resistor value must be done in conjunction with EMI compliance testing and efficiency testing. Larger R_{G} slows down the turn-on and turn-off of the MOSFET. Slower switching speed reduces EMI but also increases the switching loss. A tradeoff between switching loss and EMI performance must be carefully performed. For this design, 10 Ω was chosen as the gate driver resistor.
The precision 5-V reference voltage at REF is designed to perform several important functions. The reference voltage is divided down internally to 2.5 V and connected to the error amplifier’s noninverting input for accurate output voltage regulation. Other duties of the reference voltage are to set internal bias currents and thresholds for functions such as the oscillator upper and lower thresholds along with the overcurrent limiting threshold. Therefore, the reference voltage must be bypassed with a ceramic capacitor (C_{VREF}), and 1-µF, 16-V ceramic capacitor was selected for this converter. Placement of this capacitor on the physical printed-circuit board layout must be as close as possible to the respective REF and GND pins.
The internal oscillator uses a timing capacitor (C_{T}) and a timing resistor (R_{T}) to program operating frequency and maximum duty cycle. The operating frequency can be programmed based the curves in Figure 3, where the timing resistor can be found once the timing capacitor is selected. The selection of timing capacitor also affects the maximum duty cycle provided in Figure 5. It is best for the timing capacitor to have a flat temperature coefficient, typical of most COG or NPO type capacitors. For this converter, 1000 pF and 13.6 kΩ were selected for C_{T} and R_{T} to operate at 110-kHz switching frequency.
At start-up, the IC gets its power directly from the high voltage bulk, through a high-voltage resistor R_{H}. The selection of start-up resistor is the tradeoff between power loss and start-up time. The current flowing through R_{H} at minimum input voltage must be higher than the VCC current under UVLO condition (0.2 mA at its maximum value). A 300-kΩ resistor is chosen as the result of the tradeoff.
After VCC is charged up above the UVLO turnon threshold, UCC2813-0 starts to operate and consumes full operating current. At the beginning, because the output voltage is low, VCC cannot get energy from the auxiliary winding. The VCC capacitor is required to hold enough energy to prevent its voltage drop below UVLO during the start-up time, until the output reaches high enough. A larger capacitor holds more energy but slows down the start-up time. In this design, a 120-µF capacitor is chosen to provide enough energy for the start-up purpose.
Feedback compensation, also called closed-loop control, reduces or eliminates steady-state output voltage error, reduces the sensitivity to parametric changes, changes the gain or phase of a system over some desired frequency range, reduces the effects of small-signal load disturbances and noise on system performance, and creates a stable system. This section describes how to compensate an isolated Flyback converter with the peak-current-mode control.
The first step in compensating a fixed-frequency flyback is to verify if the converter operates in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). If the primary inductance (L_{P}) is greater than the inductance for DCM-CCM boundary mode operation, called the critical inductance (L_{Pcrit}), then the converter operates in CCM. L_{Pcrit} is calculated with Equation 17.
For loads greater than 10% of P_{MAX} over the entire input voltage range, the selected primary inductance has value larger than the critical inductance. Therefore, the converter operates in CCM and the compensation loop requires design based on CCM flyback equations.
The current-to-voltage conversion is done externally with the ground-referenced current-sense resistor (R_{CS}) and the internal resistor divider sets up the internal current-sense gain, A_{CS} = 1.65. The IC technology allows tight control of the resistor-divider ratio, regardless of the actual resistor value variations.
The DC open-loop gain (G_{O}) of the fixed-frequency voltage control loop of a peak-current-mode control CCM flyback converter shown in Figure 33 is approximated by first using the output load (R_{OUT}), the primary to secondary turns ratio (N_{PS}), and the maximum duty cycle (D) as shown in Equation 18.
where
For this design, a converter with an output voltage (V_{OUT}) of 12 V, and 48 W relates to an output load (R_{OUT}) equal to 3 Ω at full load.
At minimum input bulk voltage of 75 V DC, the duty cycle reaches its maximum value of 0.615. The current sense resistance (R_{CS}) is 0.75 Ω and a primary to secondary turns-ratio (N_{PS}) is 10. The open-loop gain calculates to 14.95 dB.
A CCM flyback transfer function has two zeroes that are of interest. The ESR and the output capacitance contribute a left-half plane zero to the power stage, and the frequency of this zero (f_{ESRz}) is calculated with Equation 22.
The f_{ESRz} zero for a capacitance bank of three 680-µF capacitors (for a total output capacitance of 2040 µF) and a total ESR of 13 mΩ is located at 6 kHz.
CCM flyback converters have a zero in the right-half plane (RHP) of their transfer function. RHP zero has the same 20 dB/decade rising gain magnitude with increasing frequency just like a left-half plane zero, but it adds phase lag instead of lead. This phase lag tends to limit the overall loop bandwidth. The frequency location (f_{RHPz}) in Equation 23 is a function of the output load, the duty cycle, the primary inductance (L_{P}), and the primary to secondary side turns ratio (N_{PS}).
RHP zero frequency increases with higher input voltage and lighter load. Generally, the design requires consideration of the worst case of the lowest RHP zero frequency and the converter must be compensated at the minimum input and maximum load condition. With a primary inductance of 1.5 mH, at 75-V DC input, the RHP zero frequency (f_{RHPz}) is equal to 7.65 kHz at maximum duty cycle (full load).
The power stage has one dominant pole (ω_{P1}) which is in the region of interest, located at a lower frequency (f_{P1}) which is related to the duty cycle (D), the output load, and the output capacitance. There is also a double pole (f_{P2}) located at half the switching frequency of the converter. These poles are frequencies calculated with Equation 24 and Equation 25.
Subharmonic oscillation is the large signal instability that can occur in CCM flyback converters when duty cycles extend beyond 50%. The subharmonic oscillation increases the output voltage ripple and sometimes it even limits the power handling capability of the converter. Slope compensation to the CS signal is a technique used to eliminate the instability.
Ideally, the target of slope compensation is to achieve quality coefficient (Q_{P} = 1) at half of the switching frequency. The Q_{P} is calculated by Equation 26.
where
where
The optimal goal of the slope compensation is to achieve Q_{P} equal to 1, which means M_{C} must be 2.128 when D reaches it maximum value of 0.615.
The inductance current slope at the CS pin is calculated by Equation 28.
The compensation slope is calculated by Equation 29.
The compensation slope is added into the system through R_{RAMP} and R_{CSF}. A series capacitor (C_{RAMP}) is selected to approximate a high-frequency short circuit. Choose C_{RAMP} as 10 nF as the starting point, and make adjustments if required. R_{RAMP} and R_{CSF} form a voltage divider to scale the RC pin ramp voltage and inject the slope compensation into CS pin. Choose R_{RAMP} much larger than the R_{T} resistor so that it does not affect the frequency setting very much. In this design, R_{RAMP} is selected as 24.9 kΩ. The RC pin ramp slope is calculated with Equation 30.
To achieve 46.3 mV/µs compensation slope, R_{CSF} resistor is calculated with Equation 31.
The power stage open-loop gain and phase can be plotted as a function of frequency. The total open-loop transfer function, as a function of frequency, can be characterized by Equation 32.
where
The open-loop gain and phase Bode plots are graphed accordingly (see Figure 34 and Figure 35).
For good transient response, the bandwidth of the finalized design must be as wide as possible. The bandwidth of a CCM flyback (f_{BW}) is limited to ¼ of the RHP-zero frequency, or approximately 1.9 kHz using Equation 33.
The gain of the open-loop power stage at f_{BW} is equal to –22.4 dB and the phase at f_{BW} is equal to –87°. First step is to choose the output voltage-sensing resistor values. The output sensing resistors are selected based on the allowed power consumption and in this case, 1 mA of sensing current is assumed.
The TL431 is used as the feedback amplifier. Given its 2.5-V reference voltage, the voltage-sensing dividers R_{FBU} and R_{FBB} can be selected with Equation 34 and Equation 35.
Next step is to put the compensator zero f_{CZ} at 190 Hz, which is 1/10 of the target crossover frequency. Choose C_{Z} as a fixed value of 10 nF and choose the zero resistor value according to Equation 36.
Next, place a pole at the lower of RHP-zero or the ESR-zero frequencies. Based previous analysis, the RHP zero is at 7.65 kHz and the ESR zero is at 6 kHz, so the pole of the compensation loop should be put at 6 kHz. This pole can be added through the primary side error amplifier. R_{FB} and C_{FB} provide the necessary pole. Choosing R_{FB} as 10 kΩ, C_{FB} is calculated by Equation 37.
Based on the compensation loop structure, the entire compensation loop transfer function is written as Equation 38.
where
The only remaining unknown value required in this equation is R_{LED}. The entire loop gain must be equal to 1 at the crossover frequency. R_{LED} is calculated accordingly as 1.62 kΩ.
The final closed-loop Bode plots are shown in Figure 36 and Figure 37. The converter achieves approximately 2-kHz crossover frequency and approximately 70° of phase margin.
TI recommends checking the loop stability across all the corner cases, including component tolerances, to ensure system stability.
100 V/div | 2 µs/div |
CH1: output voltage AC coupled | 200 mV/div | |
CH4: output current | 1 A/div | 5 ms/div |
5 V/div | 2 ms/div |
100 V/div | 2 µs/div |
100 mV/div | 10 µs/div | |