7.2.1 Current Amplifier Noninverting Input, CAI

Place a resistor between this pin and the GND side of current sense resistor. This input and the inverting input (MOUT) remain functional down to and below GND.

7.2.2 Current Amplifier Output, CAOUT

Th CAOUT pin is the output of a wide bandwidth operational amplifier that senses line current and commands the PFC pulse-width modulator (PWM) to force the correct duty cycle. Compensation components are placed between CAOUT and MOUT.

7.2.3 Oscillator Timing Capacitor, CT

A capacitor from CT to GND sets the PWM oscillator frequency according to Equation 1.

Equation 1.

The lead from the oscillator timing capacitor to GND should be as short and direct as possible.

7.2.4 Gate Drive, DRVOUT

The output drive for the boost switch is a totem-pole MOSFET gate driver on DRVOUT. Use a series gate resistor to prevent interaction between the gate impedance and the output driver that might cause the DRVOUT to overshoot excessively. See characteristic curve (Figure 13) to determine minimum required gate resister value. Some overshoot of the DRVOUT output is always expected when driving a capacitive load.

7.2.5 Ground, GND

All voltages measured with respect to ground. V_CC and REF should be bypassed directly to GND with a 0.1-μF or larger ceramic capacitor.

7.2.6 Current Proportional to Input Voltage, IAC

This input to the analog multiplier is a current proportional to instantaneous line voltage. The multiplier is tailored for very low distortion from this current input (I_IAC) to multiplier output. The recommended maximum I_IAC is 500 μA.

7.2.7 Multiplier Output and Current Amplifier Inverting Input, MOUT

The output of the analog multiplier and the inverting input of the current amplifier are connected together at MOUT. As the multiplier output is a current, this is a high-impedance input so the amplifier can be configured as a differential amplifier. This configuration improves noise immunity and allows for the leading-edge modulation operation. The multiplier output current is limited to (2 × I_IAC). The multiplier output current is given by Equation 2.

Equation 2.

where

• K = 1/V is the multiplier gain constant

7.2.8 Overvoltage and Enable, OVP/EN

A window comparator input that disables the output driver if the boost output voltage is a programmed level above the nominal, or disables both the PFC output driver and resets SS if pulled below 1.9 V (typ).

7.2.9 PFC Peak Current-Limit, PKLMT

The threshold for peak limit is 0 V. Use a resistor divider from the negative side of the current sense resistor to V_REF to level shift this signal to a voltage level defined by the value of the sense resistor and the peak current limit. Peak current limit is reached when PKLMT voltage falls below 0 V.

7.2.10 Oscillator Charging Current, RT

A resistor from RT to GND is used to program oscillator charging current. A resistor between 10 kΩ and 100 kΩ is recommended. Nominal voltage on this pin is 3 V.

7.2.11 Soft Start, SS

The V_SS supply is discharged for V_VCC low conditions. When enabled, SS charges an external capacitor with a current source. This voltage is used as the voltage error signal during start-up, enabling the PWM duty cycle to increase slowly. In the event of a V_VCC dropout, the OVP/EN is forced below 1.9 V (typical), SS quickly discharges to disable the PWM.

7.2.12 Voltage amplifier output, VAOUT

This is the output of the operational amplifier that regulates output voltage. The voltage amplifier output is internally limited to approximately 5.5 V to prevent overshoot.

7.2.13 Positive Supply Voltage, VCC

Connect to a stable source of at least 20 mA between 10 V and 17 V for normal operation. Bypass V_CC directly to GND to absorb supply current spikes required to charge external MOSFET gate capacitances. To prevent inadequate gate drive signals, the output devices are inhibited unless V_VCC exceeds the upper under-voltage lockout voltage threshold and remains above the lower threshold.

7.2.14 Feed-Forward Voltage, VFF

The RMS voltage signal generated at this pin by mirroring 1/2 of the I_IAC into a single pole external filter. At low line, the VFF voltage should be 1.4 V.

7.2.15 Voltage Amplifier Inverting Input, VSENSE

The VSENSE pin is normally connected to a compensation network and to the boost converter output through a divider network.

7.2.16 Voltage Reference Output, VREF

V_REF is the output of an accurate 7.5-V voltage reference. This output is capable of delivering 20 mA to peripheral circuitry and is internally short-circuit current limited. VREF is disabled and remains at 0 V when V_CC is below the UVLO threshold. Bypass VREF to GND with a 0.1-μF or larger ceramic capacitor for best stability. See Figure 8 and Figure 9 for VREF line and load regulation characteristics.