SLUSA16D March   2010  – November 2016 UCC28950

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Dissipation Ratings
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Start-Up Protection Logic
      2. 7.3.2  Voltage Reference (VREF)
      3. 7.3.3  Error Amplifier (EA+, EA-, COMP)
      4. 7.3.4  Soft Start and Enable (SS/EN)
      5. 7.3.5  Light-Load Power Saving Features
      6. 7.3.6  Adaptive Delay, (Delay between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 7.3.7  Adaptive Delay (Delay between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF))
      8. 7.3.8  Minimum Pulse (TMIN)
      9. 7.3.9  Burst Mode
      10. 7.3.10 Switching Frequency Setting
      11. 7.3.11 Slope Compensation (RSUM)
      12. 7.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 7.3.13 Current Sensing (CS)
      14. 7.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 7.3.15 Synchronization (SYNC)
      16. 7.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 7.3.17 Supply Voltage (VDD)
      18. 7.3.18 Ground (GND)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Power Loss Budget
        2. 8.2.2.2  Preliminary Transformer Calculations (T1)
        3. 8.2.2.3  QA, QB, QC, QD FET Selection
        4. 8.2.2.4  Selecting LS
        5. 8.2.2.5  Selecting Diodes DB and DC
        6. 8.2.2.6  Output Inductor Selection (LOUT)
        7. 8.2.2.7  Output Capacitance (COUT)
        8. 8.2.2.8  Select FETs QE and QF
        9. 8.2.2.9  Input Capacitance (CIN)
        10. 8.2.2.10 Current Sense Network (CT, RCS, R7, DA)
          1. 8.2.2.10.1 Voltage Loop Compensation Recommendation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PW Package
24-Pin TSSOP
Top View
UCC28950 pinout_lusa16.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
14 ADEL I Dead-time programming for the primary switches over CS voltage range, TABSET and TCDSET.
13 ADELEF I Delay-time programming between primary side and secondary side switches, TAFSET and TBESET.
4 COMP I/O Error amplifier output and input to the PWM comparator.
15 CS I Current sense for cycle-by-cycle over-current protection and adaptive delay functions.
12 DCM I DCM threshold setting.
6 DELAB I Dead-time delay programming between OUTA and OUTB.
7 DELCD I Dead-time delay programming between OUTC and OUTD.
8 DELEF I Delay-time programming between OUTA to OUTF, and OUTB to OUTE.
2 EA+ I Error amplifier non-inverting input.
3 EA– I Error amplifier inverting input.
24 GND — Ground. All signals are referenced to this node.
22 OUTA O 0.2-A sink/source primary switching output.
21 OUTB O 0.2-A sink/source primary switching output.
20 OUTC O 0.2-A sink/source primary switching output.
19 OUTD O 0.2-A sink/source primary switching output.
18 OUTE O 0.2-A sink/source synchronous switching output.
11 RSUM I Slope compensation programming. Voltage mode or peak current mode setting.
10 RT I Oscillator frequency set. Master or slave mode setting.
5 SS/EN I Soft-start programming, device enable and hiccup mode protection circuit.
16 SYNC I/O Synchronization out from Master controller to input of slave controller.
17 OUTF O 0.2-A sink/source synchronous switching output.
9 TMIN I Minimum duty cycle programming in burst mode.
23 VDD I Bias supply input.
1 VREF O 5-V, ±1.5%, 20-mA reference voltage output.