SLUSER8C June 2022 – March 2023 UCC28C50 , UCC28C51 , UCC28C52 , UCC28C53 , UCC28C54 , UCC28C55 , UCC28C56H , UCC28C56L , UCC28C57H , UCC28C57L , UCC28C58 , UCC28C59 , UCC38C50 , UCC38C51 , UCC38C52 , UCC38C53 , UCC38C54 , UCC38C55
PRODUCTION DATA
In certain applications, voltage mode control may be a preferred control strategy for a variety of reasons. Voltage mode control is easily executable with any current mode controller, especially the UCC28C5x family members. Implementation requires generating a 0-V to 0.9-V sawtooth shaped signal to input to the current sense pin (CS) which is also one input to the PWM comparator. This is compared to the divided down error amplifier output voltage at the other input of the PWM comparator. As the error amplifier output is varied, it intersects the sawtooth waveform at different points in time, thereby generating different pulse widths. This is a straightforward method of linearly generating a pulse whose width is proportional to the error voltage.
Implementation of voltage mode control is possible by using a fraction of the oscillator timing capacitor (CCT) waveform. This value can be divided down and fed to the current sense pin as shown in Figure 8-9. The oscillator timing components must be selected to approximate as close to a linear sawtooth waveform as possible. Although exponentially charged, large values of timing resistance and small values of timing capacitance help approximate a more linear shaped waveform. A small transistor is used to buffer the oscillator timing components from the loading of the resistive divider network. Due to the offset of the oscillator’s lower timing threshold, a DC blocking capacitor is added.