SLUSB72D March 2013 – April 2021 UCD3138064
PRODUCTION DATA
The UCD3138x (ARM7TDMI-S) is a Von-Neumann architecture, where a single bus provides access to all of the memory modules. All of the memory module addresses are sequentially aligned along the same address range.
This applies to program flash, data flash, ROM and all other peripherals. Within the UCD3138 family architecture, there is a 1024x32-bit Boot ROM that contains the initial firmware startup routines for PMBUS communication and non-volatile (FLASH) memory download. This boot ROM is executed after power-up-reset checks if there is a valid FLASH program written. If a valid program is present, the ROM code branches to the main FLASH-program execution. If there is no valid program, the device waits for a program download through the PMBus.
The UCD3138 family also supports customization of the boot program by allowing an alternative boot routine to be executed from program FLASH. This feature enables assignment of a unique address to each device; therefore, enabling firmware reprogramming even when several devices are connected on the same communication bus.
There are three separate flash memory areas present inside the device. There are 2-32 kB program flash blocks and 1-2 kB data flash area. The 32 kB program areas are organized as 8 k x 32 bit memory blocks and are intended to be for the firmware programs. The blocks are configured with page erase capability for erasing blocks as small as 1 kB per page, or with a mass erase for erasing the entire 32 kB array. The flash endurance is specified at 1000 erase/write cycles and the data retention is good for 100 years. The 2 kB data flash array is organized as a 512 x 32 bit memory (32 byte page size). The data flash is intended for firmware data value storage and data logging. Thus, the Data flash is specified as a high endurance memory of 20 k cycles with embedded error correction code (ECC).
For run time data storage and scratchpad memory, a 8 kB RAM is available. The RAM is organized as a 2 k x 32 bit array. The availability of 64 kB of program Flash memory in 2-32 kB banks, enables designers to implement multiple images of firmware (e.g. one main image + one back-up image) in the device and the flexibility to execute from either of the banks using appropriate algorithms. It also creates the unique opportunity for the processor to load a new program and subsequently execute that program without interrupting power delivery. This feature allows the end user to add new features to the power supply while eliminating any down-time required to load the new program.