9.1.1.1 Demonstration Boards

Two printed circuit boards (PCBs) are available to assist in the initial evaluation of circuit performance using the VCA820 in its two package options. Both of these are offered free of charge as unpopulated PCBs, delivered with a user's guide. The summary information for these fixtures is shown in Table 2.

The demonstration fixtures can be requested at the Texas Instruments web site (www.ti.com) through the VCA820 product folder.

9.1.1.2 Macromodels and Applications Support

Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This principle is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can play a major role in circuit performance. A SPICE model for the VCA820 is available through the TI web page. The applications group is also available for design assistance. The models available from TI predict typical small-signal ac performance, transient steps, dc performance, and noise under a wide variety of operating conditions. The models include the noise terms found in the electrical specifications of the relevant product data sheet.

9.1.2.1 Package Considerations

The VCA820 is available in both SO-14 and MSOP-10 packages. Each package has, for the different gains used in the typical characteristics, different values of R_F and R_G in order to achieve the same performance detailed in the table.

Figure 73 shows a test gain circuit for the VCA820. Table 3 lists the recommended configuration for the SO-14 and MSOP-10 package.

Figure 73. Test Circuit

Table 3. SO-14 and MSOP-10 R_F and R_G Configurations

9.2.1.1 Design Requirements

The design shown in Figure 76 supports a single-ended input, continuously variable gain control and a single-ended output. This configuration is used to achieve the best performance with a bipolar supply. This circuit also requires a maximum gain of 10 V/V and low noise.

9.2.1.2 Detailed Design Procedure

The VCA820 provides an exceptional combination of high output power capability with a wideband, greater than 40-dB gain adjust range, linear in dB variable gain amplifier. The VCA820 input stage places the transconductance element between two input buffers, using the output currents as the forward signal. As the differential input voltage rises, a signal current is generated through the gain element. This current is then mirrored and gained by a factor of two before reaching the multiplier. The other input of the multiplier is the voltage gain control pin, V_G. Depending on the voltage present on V_G, up to two times the gain current is provided to the transimpedance output stage. The transimpedance output stage is a current-feedback amplifier providing high output current capability and high slew rate, 1700 V/μs. This exceptional full-power performance comes at the price of a relatively high quiescent current (34mA), but a low input voltage noise for this type of architecture (8.2 nV/√Hz).

Figure 76 shows the dc-coupled, gain of 20 dB, dual power-supply circuit used as the basis of the ±5 V and . For test purposes, the input impedance is set to 50 Ω with a resistor to ground and the output impedance is set to 50 Ω with a series output resistor. Voltage swings reported in the table are taken directly at the input and output pins, while output power (dBm) is at the matched 50-Ω load. For the circuit in Figure 76, the total effective load is 100 Ω ∥ 1 kΩ. Note that for the SO-14 package, there is a voltage reference pin, V_REF (pin 9). For the SO-14 package, this pin must be connected to ground through a 20-Ω resistor in order to avoid possible oscillations of the output stage. In the MSOP-10 package, this pin is internally connected to ground and does not require such precaution. An X2Y® capacitor has been used for power-supply bypassing. The combination of low inductance, high resonance frequency, and integration of three capacitors in one package (two capacitors to ground and one across the supplies) of this capacitor contributes to the low second-harmonic distortion reported in the table. More information on how the VCA820 operates can be found in the section.

9.2.1.3 Application Curves

Figure 77. Small-Signal Frequency Response

Figure 78. Large-Signal Frequency Response

9.2.2.1 Design Requirements

For a difference amplifier, the design requirements are differential voltage gain, common mode rejection, and load drive capability. This circuit delivers differential gain of 2* (Rf/Rg), and CMRR as shown in Figure 80.

9.2.2.2 Detailed Design Procedure

Because both inputs of the VCA820 are high-impedance, a difference amplifier can be implemented without any major problem. This implementation is shown in Figure 79. This circuit provides excellent common-mode rejection ratio (CMRR) as long as the input is within the CMRR range of –2.1 V to +1.6 V. Note that this circuit does not make use of the gain control pin, V_G. Also, it is recommended to choose R_S such that the pole formed by R_S and the parasitic input capacitance does not limit the bandwidth of the circuit. The common-mode rejection ratio for this circuit implemented in a gain of 20 dB for V_G = +2 V is shown in Figure 80. Note that because the gain control voltage is fixed and is normally set to +2 V, the feedback element can be reduced in order to increase the bandwidth. When reducing the feedback element make sure that the VCA820 is not limited by common-mode input voltage, the current flowing through R_G, or any other limitation described in this data sheet.

9.2.2.3 Application Curve

Figure 80. Common-Mode Rejection Ratio

9.2.3.1 Design Requirements

Signals that travel over a length of cable experience an attenuation that is proportional to the square root of the frequency. For this reason, a flat response amplifier will not restore the original signal. To replicate the original signal, the higher frequency signal components require more gain. The circuit in Figure 81 has one stage of frequency shaping to help restore a signal transmitted along a cable. If needed, additional frequency shaping stages can be added as shown in Figure 82.

9.2.3.2 Detailed Design Procedure

If the application requires frequency shaping (the transition from one gain to another), the VCA820 can be used advantageously because its architecture allows the application to isolate the input from the gain setting elements. Figure 81 shows an implementation of such a configuration. The transfer function is shown in Equation 5.

Equation 5.

This transfer function has one pole, P₁ (located at R_GC₁), and one zero, Z₁ (located at R₁C₁). When equalizing an RC load, R_L and C_L, compensate the pole added by the load located at R_LC_L with the zero Z₁. Knowing R_L, C_L, and R_G allows the user to select C₁ as a first step and then calculate R₁. Using R_L = 75 Ω, C_L = 100 pF and wanting the VCA820 to operate at a gain of +2 V/V, which gives R_F = R_G = 1.33 kΩ, allows the user to select C₁ = 5 pF to ensure a positive value for the resistor R₁. With all these values known, R₁ can be calculated to be 170 Ω. The frequency response for both the initial, unequalized frequency response and the resulting equalized frequency response are illustrated in Figure 82.

9.2.3.3 Application Curve

Figure 82. Differential Equalization of an RC Load

9.2.4.1 Design Requirements

Signals that travel over a length of cable experience an attenuation that is proportional to the square root of the frequency. For this reason, a fixed bandwidth amplifier will not restore the original signal. To replicate the original signal, the higher frequency signal components require more gain. The circuit in Figure 83 has multiple stages of frequency shaping to help restore a signal transmitted along a cable. This circuit is similar to the one shown in Figure 81, but is much more accurate in replicating the 1/(sqrt(f)) frequency response shape.

9.2.4.2 Detailed Design Procedure

A differential cable equalizer can easily be implemented using the VCA820. An example of a cable equalization for 100 feet of Belden Cable 1694F is illustrated in Figure 83, with the result for this implementation shown in Figure 84. This implementation has a maximum error of 0.2 dB from dc to 40 MHz.

Note that this implementation shows the cable attenuation side-by-side with the equalization in the same plot. For a given frequency, the equalization function realized with the VCA820 matches the cable attenuation. The circuit in Figure 83 is a driver circuit. To implement a receiver circuit, the signal is received differentially between the +V_IN and –V_IN inputs.

For a detailed design procedure, refer to to SBOA124.

9.2.4.3 Application Curve

Figure 84. Cable Attenuation versus Equalizer Gain

9.2.5.1 Design Requirements

When dynamic signal amplitude correction is required, an AGC loop will provide real-time gain control. The requirements for this circuit are fast gain control response and linear in dB gain control. The time constant of the loop is set with the 0.1-µF capacitor and the 1-kΩ resistor. The OPA695 provides additional load driving capability.

9.2.5.2 Detailed Design Procedure

In the typical AGC loop shown in Figure 85, the OPA695 follows the VCA820 to provide 40 dB of overall gain. The output of the OPA695 is rectified and integrated by an OPA820 to control the gain of the VCA820. When the output level exceeds the reference voltage (V_REF), the integrator ramps down reducing the gain of the AGC loop. Conversely, if the output is too small, the integrator ramps up increasing the net gain and the output voltage.