JAJSAD1G April   2005  – May 2016 ADC081S021

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Determining Throughput
    4. 8.4 Device Functional Modes
      1. 8.4.1 Transfer Function
      2. 8.4.2 Modes of Operation
        1. 8.4.2.1 Normal Mode
        2. 8.4.2.2 Shutdown Mode
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Inputs
      2. 9.1.2 Digital Inputs and Outputs
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Noise Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの関連用語
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

10 Power Supply Recommendations

The ADC takes time to power up, either after first applying VA, or after returning to normal mode from shutdown mode. This corresponds to one dummy conversion for any SCLK frequency within the specifications in this document. After this first dummy conversion, the ADC performs conversions properly.

NOTE

The tQUIET time must still be included between the first dummy conversion and the second valid conversion.

When the VA supply is first applied, the ADC may power up in either of the two modes: normal or shutdown. As such, one dummy conversion must be performed after start-up, as described in the previous paragraph. The part may then be placed into either normal mode or the shutdown mode, as described in Normal Mode and Shutdown Mode.

When the ADC is operated continuously in normal mode, the maximum ensured throughput is fSCLK / 20 at the maximum specified fSCLK. Throughput may be traded for power consumption by running fSCLK at its maximum specified rate and performing fewer conversions per unit time, raising the ADC CS line after the 10th and before the 15th fall of SCLK of each conversion. A plot of typical power consumption versus throughput is shown in Typical Characteristics. To calculate the power consumption for a given throughput, multiply the fraction of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption. The curve of power consumption vs throughput (Figure 17) is essentially linear. This is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes.

10.1 Noise Considerations

The charging of any output load capacitance requires current from the power supply, VA. The current pulses required from the supply to charge the output capacitance causes voltage variations on the supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic low dumps current into the die substrate, which is resistive. Load discharge currents cause ground bounce noise in the substrate that degrades noise performance if that current is large enough. The larger the output capacitance, the more current flows through the die substrate and the greater is the noise coupled into the analog channel, degrading noise performance.

To keep noise out of the power supply, keep the output load capacitance as small as practical. It is good practice to use a 100-Ω series resistor at the ADC output, placed as close to the ADC output pin as practical. This limits the charge and discharge current of the output capacitance and maintain noise performance.