JAJSA99F April   2005  – July 2016 ADC084S021

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transfer Function
      2. 8.3.2 Analog Inputs
      3. 8.3.3 Digital Inputs and Outputs
    4. 8.4 Device Functional Modes
      1. 8.4.1 Track Mode
      2. 8.4.2 Hold Mode
    5. 8.5 Register Maps
      1. 8.5.1 Register Description
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power Management
    2. 10.2 Noise Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの関連用語
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

DGK Package
10-Pin VSSOP
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 CS I Chip select. A conversion begins at the falling edge of CS. Conversions continue as long as CS is held low.
2 VA — Positive supply pin. This pin must be connected to a quiet 2.7-V to 5.25-V source and be bypassed to GND with a 0.1-µF monolithic capacitor located within 1 cm of the power pin and with a 1-µF capacitor.
3 GND — Device ground return for all signals.
4, 5, 6, 7 IN1 to IN4 I Analog inputs. These signals can range from 0 V to VA.
8 DIN I Digital data input. The ADC084S021's control register is loaded through this pin on rising edges of SCLK.
9 DOUT O Digital data output. The output samples are clocked out at this pin on falling edges of the SCLK pin.
10 SCLK I Digital clock input. This clock directly controls the conversion and readout processes.