JAJSOE7C June 2022 – March 2023 ADC12DJ5200-EP
PRODUCTION DATA
Table 7-63 lists the SPI_Register_Map registers. All register offset addresses not listed in Table 7-63 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Section |
---|---|---|---|
0x0 | CONFIG_A | Configuration A (default: 0x30) | Go |
0x2 | DEVICE_CONFIG | Device Configuration (default: 0x00) | Go |
0x3 | CHIP_TYPE | Chip Type (Default: 0x03) | Go |
0x4 | CHIP_ID | Chip Identification | Go |
0xC | VENDOR_ID | Vendor Identification (Default = 0x0451) | Go |
0x10 | USR0 | User SPI Configuration (Default: 0x00) | Go |
0x29 | CLK_CTRL0 | Clock Control 0 (default: 0x00) | Go |
0x2A | CLK_CTRL1 | Clock Control 1 (default: 0x00) | Go |
0x02B | CLK_CNTL2 | Clock Control 2 (default: 0x11) | Go |
0x2C | SYSREF_POS | SYSREF Capture Position (Read-Only, Default: undefined) | Go |
0x30 | FS_RANGE_A | FS_RANGE_A (default: 0xA000) | Go |
0x32 | FS_RANGE_B | FS_RANGE_B (default: 0xA000) | Go |
0x38 | BG_BYPASS | Band-Gap Bypass (default: 0x00) | Go |
0x3B | TMSTP_CTRL | TMSTP Control (default: 0x00) | Go |
0x48 | SER_PE | Serializer Pre-Emphasis Control (default: 0x00) | Go |
0x60 | INPUT_MUX | Input Mux Control (default: 0x01) | Go |
0x61 | CAL_EN | Calibration Enable (Default: 0x01) | Go |
0x62 | CAL_CFG0 | Calibration Configuration 0 (Default: 0x01) | Go |
0x64 | CAL_CFG2 | Calibration Configuration 0 (Default: 0x02) | Go |
0x68 | CAL_AVG | Calibration Averaging (default: 0x61) | Go |
0x6A | CAL_STATUS | Calibration Status (default: undefined) (read-only) | Go |
0x6B | CAL_PIN_CFG | Calibration Pin Configuration (default: 0x00) | Go |
0x6C | CAL_SOFT_TRIG | Calibration Software Trigger (default: 0x01) | Go |
0x6E | CAL_LP | Low-Power Background Calibration (default: 0x88) | Go |
0x70 | CAL_DATA_EN | Calibration Data Enable (default: 0x00) | Go |
0x71 | CAL_DATA | Calibration Data (default: undefined) | Go |
0x7A | GAIN_TRIM_A | Gain DAC Trim A (default from Fuse ROM) | Go |
0x7B | GAIN_TRIM_B | Gain DAC Trim B (default from Fuse ROM) | Go |
0x7C | BG_TRIM | Band-Gap Trim (default from Fuse ROM) | Go |
0x7E | RTRIM_A | Resistor Trim for VinA (default from Fuse ROM) | Go |
0x7F | RTRIM_B | Resistor Trim for VinB (default from Fuse ROM) | Go |
0x9D | ADC_DITH | ADC Dither Control (default from Fuse ROM) | Go |
0x160 | LSB_CTRL | LSB Control Bit Output (default: 0x00) | Go |
0x200 | JESD_EN | JESD204C Subsystem Enable (default: 0x01) | Go |
0x201 | JMODE | JESD204C Mode (default: 0x02) | Go |
0x202 | KM1 | JESD204C K Parameter (default: 0x1F) | Go |
0x203 | JSYNC_N | JESD204C Manual Sync Request (default: 0x01) | Go |
0x204 | JCTRL | JESD204C Control (default: 0x03) | Go |
0x205 | JTEST | JESD204C Test Control (default: 0x00) | Go |
0x206 | DID | JESD204C DID Parameter (default: 0x00) | Go |
0x207 | FCHAR | JESD204C Frame Character (default: 0x00) | Go |
0x208 | JESD_STATUS | JESD204C / System Status Register | Go |
0x209 | PD_CH | JESD204C Channel Power Down (default: 0x00) | Go |
0x20A | JEXTRA_A | JESD204C Extra Lane Enable (Link A) (default: 0x00) | Go |
0x20B | JEXTRA_B | JESD204C Extra Lane Enable (Link B) (default: 0x00) | Go |
0x20F | SHMODE | JESD204C Sync Word Mode (default: 0x00) | Go |
0x210 | DDC_CFG | DDC Configuration (default: 0x00) | Go |
0x211 | OVR_T0 | Over-range Threshold 0 (default: 0xF2) | Go |
0x212 | OVR_T1 | Over-range Threshold 1 (default: 0xAB) | Go |
0x213 | OVR_CFG | Over-range Enable / Hold Off (default: 0x07) | Go |
0x214 | CMODE | DDC NCO Configuration Preset Mode (default: 0x00) | Go |
0x215 | CSEL | DDC NCO Configuration Preset Select (default: 0x00) | Go |
0x216 | DIG_BIND | Digital Channel Binding (default: 0x02) | Go |
0x217 | NCO_RDIV | NCO Reference Divisor (default: 0x0000) | Go |
0x219 | NCO_SYNC | NCO Synchronization (default: 0x02) | Go |
0x220 | FREQA0 | NCO Frequency (Channel A, Preset 0) (default: 0xC0000000) | Go |
0x224 | PHASEA0 | NCO Phase (Channel A, Preset 0) (default: 0x0000) | Go |
0x228 | FREQA1 | NCO Frequency (Channel A, Preset 1) (default: 0xC0000000) | Go |
0x22C | PHASEA1 | NCO Phase (Channel A, Preset 1) (default: 0x0000) | Go |
0x230 | FREQA2 | NCO Frequency (Channel A, Preset 2) (default: 0xC0000000) | Go |
0x234 | PHASEA2 | NCO Phase (Channel A, Preset 2) (default: 0x0000) | Go |
0x238 | FREQA3 | NCO Frequency (Channel A, Preset 3) (default: 0xC0000000) | Go |
0x23C | PHASEA3 | NCO Phase (Channel A, Preset 3) (default: 0x0000) | Go |
0x240 | FREQB0 | NCO Frequency (Channel B, Preset 0) (default: 0xC0000000) | Go |
0x244 | PHASEB0 | NCO Phase (Channel B, Preset 0) (default: 0x0000) | Go |
0x248 | FREQB1 | NCO Frequency (Channel B, Preset 1) (default: 0xC0000000) | Go |
0x24C | PHASEB1 | NCO Phase (Channel B, Preset 1) (default: 0x0000) | Go |
0x250 | FREQB2 | NCO Frequency (Channel B, Preset 2) (default: 0xC0000000) | Go |
0x254 | PHASEB2 | NCO Phase (Channel B, Preset 2) (default: 0x0000) | Go |
0x258 | FREQB3 | NCO Frequency (Channel B, Preset 3) (default: 0xC0000000) | Go |
0x25C | PHASEB3 | NCO Phase (Channel B, Preset 3) (default: 0x0000) | Go |
0x270 | INIT_STATUS | Initialization Status (read-only) | Go |
0x297 | SPIN_ID | Chip Spin Identifier (default: See description, read-only) | Go |
0x2A2 | TESTBUS | Analog Test Bus Control (default: 0x00) | Go |
0x2B0 | SRC_EN | SYSREF Calibration Enable (default: 0x00) | Go |
0x2B1 | SRC_CFG | SYSREF Calibration Configuration (default: 0x05) | Go |
0x2B2 | SRC_STATUS | SYSREF Calibration Status (read-only, default: undefined) | Go |
0x2B5 | TAD | DEVCLK Timing Adjust (default: 0x00) | Go |
0x2B8 | TAD_RAMP | DEVCLK Timing Adjust Ramp Control (default: 0x00) | Go |
0x2C0 | ALARM | Alarm Interrupt (read-only) | Go |
0x2C1 | ALM_STATUS | Alarm Status (default: 0x3F, write to clear) | Go |
0x2C2 | ALM_MASK | Alarm Mask Register (default: 0x3F) | Go |
0x2C4 | FIFO_LANE_ALM | FIFO Overflow/Underflow Alarm (default: 0xFFFF) | Go |
0x310 | TADJ_A | Timing Adjust for A-ADC operating in Dual Channel Mode (default from Fuse ROM) | Go |
0x313 | TADJ_B | Timing Adjust for B-ADC operating in Dual Channel Mode (default from Fuse ROM) | Go |
0x314 | TADJ_A_FG90_VINA | Timing Adjust for A-ADC operating in Single Channel Mode and sampling INA± (default from Fuse ROM) | Go |
0x315 | TADJ_B_FG0_VINA | Timing Adjust for B-ADC operating in Single Channel Mode and sampling INA± (default from Fuse ROM) | Go |
0x31A | TADJ_A_FG90_VINB | Timing Adjust for A-ADC operating in Single Channel Mode and sampling INB± (default from Fuse ROM) | Go |
0x31B | TADJ_B_FG0_VINB | Timing Adjust for B-ADC operating in Single Channel Mode and sampling INB± (default from Fuse ROM) | Go |
0x344 | OADJ_A_FG0_VINA | Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INA± (default from Fuse ROM) | Go |
0x346 | OADJ_A_FG0_VINB | Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INB± (default from Fuse ROM) | Go |
0x348 | OADJ_A_FG90_VINA | Offset Adjustment for A-ADC operating in Single Channel Mode sampling INA± (default from Fuse ROM) | Go |
0x34A | OADJ_A_FG90_VINB | Offset Adjustment for A-ADC operating in Single Channel Mode sampling INB± (default from Fuse ROM) | Go |
0x34C | OADJ_B_FG0_VINA | Offset Adjustment for B-ADC sampling INA± (default from Fuse ROM) | Go |
0x34E | OADJ_B_FG0_VINB | Offset Adjustment for B-ADC sampling INB± (default from Fuse ROM) | Go |
0x350 | GAIN_A0_FGDUAL | Fine Gain Adjust for ADC A Bank 0 in Dual Channel Mode (default from Fuse ROM) | Go |
0x351 | GAIN_A1_FGDUAL | Fine Gain Adjust for ADC A Bank 1 in Dual Channel Mode (default from Fuse ROM) | Go |
0x352 | GAIN_B0_FGDUAL | Fine Gain Adjust for ADC B Bank 0 in Dual Channel Mode (default from Fuse ROM) | Go |
0x353 | GAIN_B1_FGDUAL | Fine Gain Adjust for ADC B Bank 1 in Dual Channel Mode (default from Fuse ROM) | Go |
0x354 | GAIN_A0_FGDES | Fine Gain Adjust for ADC A Bank 0 in Single Channel Mode (default from Fuse ROM) | Go |
0x355 | GAIN_A1_FGDES | Fine Gain Adjust for ADC A Bank 1 in Single Channel Mode (default from Fuse ROM) | Go |
0x356 | GAIN_B0_FGDES | Fine Gain Adjust for ADC B Bank 0 in Single Channel Mode (default from Fuse ROM) | Go |
0x357 | GAIN_B1_FGDES | Fine Gain Adjust for ADC B Bank 1 in Single Channel Mode (default from Fuse ROM) | Go |
0x400 | PFIR_CFG | Programmable FIR Mode (default: 0x00) | Go |
0x418 | PFIR_A0 | PFIR Coefficient A0 | Go |
0x41A | PFIR_A1 | PFIR Coefficient A1 | Go |
0x41C | PFIR_A2 | PFIR Coefficient A2 | Go |
0x41E | PFIR_A3 | PFIR Coefficient A3 | Go |
0x420 | PFIR_A4 | PFIR Coefficient A4 | Go |
0x423 | PFIR_A5 | PFIR Coefficient A5 | Go |
0x425 | PFIR_A6 | PFIR Coefficient A6 | Go |
0x427 | PFIR_A7 | PFIR Coefficient A7 | Go |
0x429 | PFIR_A8 | PFIR Coefficient A8 | Go |
0x448 | PFIR_B0 | PFIR Coefficient B0 | Go |
0x44A | PFIR_B1 | PFIR Coefficient B1 | Go |
0x44C | PFIR_B2 | PFIR Coefficient B2 | Go |
0x44E | PFIR_B3 | PFIR Coefficient B3 | Go |
0x450 | PFIR_B4 | PFIR Coefficient B4 | Go |
0x453 | PFIR_B5 | PFIR Coefficient B5 | Go |
0x455 | PFIR_B6 | PFIR Coefficient B6 | Go |
0x457 | PFIR_B7 | PFIR Coefficient B7 | Go |
0x459 | PFIR_B8 | PFIR Coefficient B8 | Go |
Complex bit access types are encoded to fit into small table cells. Table 7-64 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
CONFIG_A is shown in Figure 7-28 and described in Table 7-65.
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Configuration A (default: 0x30)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SOFT_RESET | RESERVED | ASCEND | SDO_ACTIVE | RESERVED | |||
R/W-0x0 | R/W-0x0 | R/W-0x1 | R-0x1 | R/W-0x0 | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SOFT_RESET | R/W | 0x0 | Setting this bit causes a full reset of the chip and all SPI registers (including CONFIG_A). This bit is self-clearing. After writing this bit, the part may take up to 750ns to reset. During this time, do not perform any SPI transactions. |
6 | RESERVED | R/W | 0x0 | |
5 | ASCEND | R/W | 0x1 | 0 : Address is decremented during streaming reads/writes |
4 | SDO_ACTIVE | R | 0x1 | Always returns 1. Always use SDO for SPI reads. |
3:0 | RESERVED | R/W | 0x0 |
DEVICE_CONFIG is shown in Figure 7-29 and described in Table 7-66.
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Device Configuration (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MODE | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | RESERVED | R/W | 0x0 | |
1:0 | MODE | R/W | 0x0 | 0 : Normal operation (default) |
CHIP_TYPE is shown in Figure 7-30 and described in Table 7-67.
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Chip Type (Default: 0x03)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CHIP_TYPE | ||||||
R/W-0x0 | R-0x3 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | RESERVED | R/W | 0x0 | |
3:0 | CHIP_TYPE | R | 0x3 | Always returns 0x3, indicating that the part is a high speed ADC. |
CHIP_ID is shown in Figure 7-31 and described in Table 7-68.
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Chip Identification
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CHIP_ID | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHIP_ID | |||||||
R-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | CHIP_ID | R | 0x0 | Returns 0x0021 indicating the device is in the ADCrrDJssssRF family. |
VENDOR_ID is shown in Figure 7-32 and described in Table 7-69.
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Vendor Identification (Default = 0x0451)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
VENDOR_ID | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VENDOR_ID | |||||||
R-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | VENDOR_ID | R | 0x0 | Always returns 0x0451 (Vendor ID for Texas Instruments) |
USR0 is shown in Figure 7-33 and described in Table 7-70.
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User SPI Configuration (Default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR_HOLD | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | RESERVED | R/W | 0x0 | |
0 | ADDR_HOLD | R/W | 0x0 | 0 : Use ASCEND register to select address ascend/descend mode (default) |
CLK_CTRL0 is shown in Figure 7-34 and described in Table 7-71.
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Clock Control 0 (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SYSREF_PROC_EN | SYSREF_RECV_EN | SYSREF_ZOOM | SYSREF_SEL | |||
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0x0 | |
6 | SYSREF_PROC_EN | R/W | 0x0 | This bit enables the SYSREF processor, which allows the device to process SYSREF events (default: disabled). SYSREF_RECV_EN must be set before setting SYSREF_PROC_EN. |
5 | SYSREF_RECV_EN | R/W | 0x0 | Set this bit to enable the SYSREF receiver circuit (default: disabled) |
4 | SYSREF_ZOOM | R/W | 0x0 | Set this bit to zoom in the SYSREF windowing status and delays (impacts SYSERF_POS and SYSREF_SEL). When set, the delays used in the SYSREF windowing feature (reported in the SYSREF_POS register) become smaller. Use SYSREF_ZOOM for high clock rates, specifically when multiple SYSREF valid windows are encountered in the SYSREF_POS register; see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section. |
3:0 | SYSREF_SEL | R/W | 0x0 | Set this field to select which SYSREF delay to use. Set this field based on the results returned by SYSREF_POS; see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section. These bits must be set to 0 to use SYSREF calibration; see the Automatic SYSREF Calibration section. |
CLK_CTRL1 is shown in Figure 7-35 and described in Table 7-72.
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Clock Control 1 (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SYSREF_TIME_STAMP_EN | DEVCLK_LVPECL_EN | SYSREF_LVPECL_EN | SYSREF_INVERTED | |||
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | RESERVED | R/W | 0x0 | |
3 | SYSREF_TIME_STAMP_EN | R/W | 0x0 | The SYSREF signal can be observed on the LSB of the JESD204C output samples when SYSREF_TIMESTAMP_EN and TIME_STAMP_EN are both set. Only supported in DDC bypass modes (that is, D=1). This bit allows SYSREF± to be used as the timestamp input. |
2 | DEVCLK_LVPECL_EN | R/W | 0x0 | Activate DC-coupled, low-voltage PECL mode for CLK±; see the Pin Functions table. |
1 | SYSREF_LVPECL_EN | R/W | 0x0 | Activate DC-coupled, low-voltage PECL mode for SYSREF±; see the Pin Functions table. |
0 | SYSREF_INVERTED | R/W | 0x0 | This bit inverts the SYSREF signal used for alignment. |
CLK_CTRL2 is shown in and described in Figure 7-36 and described in Table 7-73.
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Clock Control 2 (default: 0x11)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | C_CLK_FEEDBACK_GAIN | Reserved | EN_VA11_NOISE_SUPPR | CLKSAMP_DEL | |||
R/W-0x0 | R/W-0x1 | R/W-0x0 | R/W-0x0 | R/W-0x1 | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R/W | 0x0 | |
4 | C_CLK_FEEDBACK_GAIN | R/W | 0x1 | Adjustable feedback gain for CMLtoCMOS converter (high gain:1) |
3 | Reserved | R/W | 0x0 | Reserved |
2 | EN_VA11_NOISE_SUPPR | R/W | 0x0 | When set, noise on VA11 is suppressed. It is recommended to have this set, as it reduces noise coupling from the digital circuits to analog clock, at the expense of a small increase in power. |
1:0 | CLKSAMP_DEL | R/W | 0x1 | Adjustable delay for the sampling clock (one hot encoded) |
SYSREF_POS is shown in Figure 7-37 and described in Table 7-74.
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SYSREF Capture Position (Read-Only, Default: undefined)
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SYSREF_POS | |||||||
R/W-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SYSREF_POS | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SYSREF_POS | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
23:0 | SYSREF_POS | R/W | 0x0 | Returns a 24-bit status value that indicates the position of the SYSREF edge with respect to CLK±. Use this to program SYSREF_SEL. |
FS_RANGE_A is shown in Figure 7-38 and described in Table 7-75.
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FS_RANGE_A (default: 0xA000)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FS_RANGE_A | |||||||
R/W-0xA000 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FS_RANGE_A | |||||||
R/W-0xA000 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | FS_RANGE_A | R/W | 0xA000 | These bits enable adjustment of the analog full-scale range for INA±. 0x0000: Settings below 0x2000 result in degraded performance 0x2000: 500 mVPP - Recommended minimum setting 0xA000: 800 mVPP (default) 0xFFFF: 1000 mVPP - Maximum setting |
FS_RANGE_B is shown in Figure 7-39 and described in Table 7-76.
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FS_RANGE_B (default: 0xA000)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FS_RANGE_B | |||||||
R/W-0xA000 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FS_RANGE_B | |||||||
R/W-0xA000 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | FS_RANGE_B | R/W | 0xA000 | These bits enable adjustment of the analog full-scale range for INB±. 0x0000: Settings below 0x2000 result in degraded performance 0x2000: 500 mVPP - Recommended minimum setting 0xA000: 800 mVPP (default) 0xFFFF: 1000 mVPP - Maximum setting |
BG_BYPASS is shown in Figure 7-40 and described in Table 7-77.
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Band-Gap Bypass (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BG_BYPASS | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | RESERVED | R/W | 0x0 | |
0 | BG_BYPASS | R/W | 0x0 | When set, VA11 is used as the voltage reference instead of the band-gap voltage. |
TMSTP_CTRL is shown in Figure 7-41 and described in Table 7-78.
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TMSTP Control (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TMSTP_LVPECL_EN | TMSTP_RECV_EN | |||||
R/W-0x0 | R/W-0x0 | R/W-0x0 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | RESERVED | R/W | 0x0 | |
1 | TMSTP_LVPECL_EN | R/W | 0x0 | When set, activates the low voltage PECL mode for the differential TMSTP± input. |
0 | TMSTP_RECV_EN | R/W | 0x0 | Enables the differential differential TMSTP± input. |
SER_PE is shown in Figure 7-42 and described in Table 7-79.
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Serializer Pre-Emphasis Control (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SER_PE_BOOST | SER_PE | |||||
R/W-0x0 | R/W-0x0 | R/W-0x0 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | RESERVED | R/W | 0x0 | |
3 | SER_PE_BOOST | R/W | 0x0 | Additional pre-emphesis boost that increases the pre-emphesis slightly and extends it in time. |
2:0 | SER_PE | R/W | 0x0 | Sets the pre-emphasis for the SerDes output lanes. Pre-emphasis can be used to compensate for the high-frequency loss of the PCB trace. This is a global setting that affects all 16 lanes (DA[7:0]±, DB[7:0]±). |
INPUT_MUX is shown in Figure 7-43 and described in Table 7-80.
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Input Mux Control (default: 0x01)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DUAL_INPUT | RESERVED | SINGLE_INPUT | ||||
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x1 | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R/W | 0x0 | |
4 | DUAL_INPUT | R/W | 0x0 | Select inputs for dual channel modes. If JMODE is selecting a single channel mode, this register has no effect. 0: A channel samples INA±, B channel samples INB± (no swap) (default) 1: A channel samples INB±, B channel samples INA± (swap) |
3:2 | RESERVED | R/W | 0x0 | |
1:0 | SINGLE_INPUT | R/W | 0x1 | Defines which input is sampled in single channel mode. If JMODE is not selecting a single channel mode, this register has no effect. 0: RESERVED 1: INA± is used (default) 2: INB± is used 3: ADC channel A samples INA± and ADC channel B samples INB± (DUAL DES mode). A calibration needs to be performance after switching the input mux for the changes to take effect. |
CAL_EN is shown in Figure 7-44 and described in Table 7-81.
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Calibration Enable (Default: 0x01)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CAL_EN | ||||||
R/W-0x0 | R/W-0x1 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | RESERVED | R/W | 0x0 | |
0 | CAL_EN | R/W | 0x1 | Calibration Enable. Set high to run calibration. Set low to hold calibration in reset to program new calibration settings. Clearing CAL_EN also resets the clock dividers that clock the digital block and JESD204C interface. Some calibration registers require clearing CAL_EN before making any changes. All registers with this requirement contain a note in their descriptions. After changing the registers, set CAL_EN to re-run calibration with the new settings. Always set CAL_EN before setting JESD_EN. Always clear JESD_EN before clearing CAL_EN. |
CAL_CFG0 is shown in Figure 7-45 and described in Table 7-82.
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Calibration Configuration 0 (Default: 0x01)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CAL_BGOS | CAL_OS | CAL_BG | CAL_FG | |||
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x1 | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | RESERVED | R/W | 0x0 | |
3 | CAL_BGOS | R/W | 0x0 | 0 : Disable background offset calibration (default) 1 : Enable background offset calibration (requires CAL_BG to be set). |
2 | CAL_OS | R/W | 0x0 | 0 : Disable foreground offset calibration (default) 1 : Enable foreground offset calibration (requires CAL_FG to be set). |
1 | CAL_BG | R/W | 0x0 | 0 : Disable background calibration (default) 1 : Enable background calibration |
0 | CAL_FG | R/W | 0x1 | 0 : Reset calibration values, skip foreground calibration. 1 : Reset calibration values, then run foreground calibration (default). |
CAL_CFG2 is shown in Figure 7-46and described in Table 7-83.
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Calibration Configuration 2 (Default: 0x02)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADC_OFF | ||||||
R/W-0x00 | R/W-0x10 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | RESERVED | R/W | 0x00 | Reserved |
1:0 | ADC_OFF | R/W | 0x1 | If background calibration is disabled, this selects which ADC will be disabled and never calibrated. Only change ADC_OFF while JESD_EN is 0. 0 : ADC0 (ADC1 will stand in for ADC0) 1 : ADC1 2 : ADC2 (ADC1 will stand in for ADC2) 3 : Reserved |
CAL_AVG is shown in Figure 7-47 and described in Table 7-84.
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Calibration Averaging (default: 0x61)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OS_AVG | RESERVED | CAL_AVG | ||||
R/W-0x0 | R/W-0x6 | R/W-0x0 | R/W-0x1 | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0x0 | |
6:4 | OS_AVG | R/W | 0x6 | Select the amount of averaging used for the offset correction routine. A larger number corresponds to more averaging. |
3 | RESERVED | R/W | 0x0 | |
2:0 | CAL_AVG | R/W | 0x1 | Select the amount of averaging used for the linearity calibration routine. A larger number corresponds to more averaging. |
CAL_STATUS is shown in Figure 7-48 and described in Table 7-85.
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Calibration Status (default: undefined) (read-only)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CAL_STAT | CAL_STOPPED | FG_DONE | ||||
R-0x0 | R-0x0 | R-0x0 | R-0x0 | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R | 0x0 | |
4:2 | CAL_STAT | R | 0x0 | Calibration status code |
1 | CAL_STOPPED | R | 0x0 | This bit returns a 1 when background calibration is successfully stopped at the requested phase. This bit returns a 0 when calibration starts operating again. If background calibration is disabled, this bit is set when foreground calibration is completed or skipped. |
0 | FG_DONE | R | 0x0 | This bit is high to indicate that foreground calibration has completed (or was skipped). |
CAL_PIN_CFG is shown in Figure 7-49 and described in Table 7-86.
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Calibration Pin Configuration (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CAL_STATUS_SEL | CAL_TRIG_EN | |||||
R/W-0x0 | R/W-0x0 | R/W-0x0 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:3 | RESERVED | R/W | 0x0 | |
2:1 | CAL_STATUS_SEL | R/W | 0x0 | 0 : CALSTAT output matches FG_DONE. 1 : CALSTAT output matches CAL_STOPPED. 2 : CALSTAT output matches ALARM. 3 : CALSTAT output is always low. |
0 | CAL_TRIG_EN | R/W | 0x0 | This bit selects the hardware or software trigger source. 0 : Use the CAL_SOFT_TRIG register for the calibration trigger. The CALTRIG input is disabled (ignored). 1 : Use the CALTRIG input for the calibration trigger. The CAL_SOFT_TRIG register is ignored. |
CAL_SOFT_TRIG is shown in Figure 7-50 and described in Table 7-87.
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Calibration Software Trigger (default: 0x01)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CAL_SOFT_TRIG | ||||||
R/W-0x0 | R/W-0x1 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | RESERVED | R/W | 0x0 | |
0 | CAL_SOFT_TRIG | R/W | 0x1 | CAL_SOFT_TRIG is a software bit to provide the functionality of the CALTRIG input pin when there are no hardware resources to drive CALTRIG. Program CAL_TRIG_EN=0 to use CAL_SOFT_TRIG for the calibration trigger. |
CAL_LP is shown in Figure 7-51 and described in Table 7-88.
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Low-Power Background Calibration (default: 0x88)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LP_SLEEP_DLY | LP_WAKE_DLY | RESERVED | LP_TRIG | LP_EN | |||
R/W-0x4 | R/W-0x1 | R/W-0x0 | R/W-0x0 | R/W-0x0 | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | LP_SLEEP_DLY | R/W | 0x4 | These bits adjust how long an ADC sleeps before
waking for calibration (only applies when LP_EN = 1 and LP_TRIG
= 0). Values below 4 are not recommended because of limited
overall power reduction benefits. |
4:3 | LP_WAKE_DLY | R/W | 0x1 | These bits adjust how much time is provided for
settling before calibrating an ADC after the ADC wakes up (only
applies when LP_EN = 1). Values lower than 1 are not recommended
because there is insufficient time for the core to stabilize
before calibration begins. |
2 | RESERVED | R/W | 0x0 | |
1 | LP_TRIG | R/W | 0x0 | 0 : ADC sleep duration is set by LP_SLEEP_DLY (autonomous mode). |
0 | LP_EN | R/W | 0x0 | 0 : Disable low-power background calibration (default) |
CAL_DATA_EN is shown in Figure 7-52 and described in Table 7-89.
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Calibration Data Enable (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CAL_DATA_EN | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | RESERVED | R/W | 0x0 | |
0 | CAL_DATA_EN | R/W | 0x0 | Set this bit to enable the CAL_DATA register to enable reading and writing of calibration data; see the CAL_DATA register for more information. |
CAL_DATA is shown in Figure 7-53 and described in Table 7-90.
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Calibration Data (default: undefined)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAL_DATA | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | CAL_DATA | R/W | 0x0 | After setting CAL_DATA_EN, repeated reads of this register return all calibration values for the ADCs. Repeated writes of this register input all calibration values for the ADCs. To read the calibration data, read the register 673 times. To write the vector, write the register 673 times with previously stored calibration data. To speed up the read or write operation, set ADDR_HOLD = 1 and use streaming read or write process. |
GAIN_TRIM_A is shown in Figure 7-54 and described in Table 7-91.
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Gain DAC Trim A (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GAIN_TRIM_A | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | GAIN_TRIM_A | R/W | 0x0 | This register enables gain trim of INA±. After reset, the factory trimmed value can be read and adjusted as required. Use FS_RANGE_A to adjust the analog full-scale voltage (Vfs) of INA±. |
GAIN_TRIM_B is shown in Figure 7-55 and described in Table 7-92.
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Gain DAC Trim B (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GAIN_TRIM_B | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | GAIN_TRIM_B | R/W | 0x0 | This register enables gain trim of INB±. After reset, the factory trimmed value can be read and adjusted as required. Use FS_RANGE_B to adjust the analog full-scale voltage (Vfs) of INB±. |
BG_TRIM is shown in Figure 7-56 and described in Table 7-93.
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Band-Gap Trim (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BG_TRIM | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | RESERVED | R/W | 0x0 | |
3:0 | BG_TRIM | R/W | 0x0 | This register enables trimming of the internal band-gap reference. After reset, the factory trimmed value can be read and adjusted as required. |
RTRIM_A is shown in Figure 7-57 and described in Table 7-94.
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Resistor Trim for VinA (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTRIM_A | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | RTRIM_A | R/W | 0x0 | This register controls the INA± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required. |
RTRIM_B is shown in Figure 7-58 and described in Table 7-95.
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Resistor Trim for VinB (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTRIM_B | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | RTRIM_B | R/W | 0x0 | This register controls the INB± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required. |
ADC_DITH is shown in Figure 7-59 and described in Table 7-96.
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ADC Dither Control (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADC_DITH_ERR | ADC_DITH_AMP | ADC_DITH_EN | ||||
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x1 | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:3 | RESERVED | R/W | 0x0 | |
2 | ADC_DITH_ERR | R/W | 0x0 | Small rounding errors may occur when subtracting the dither signal. The error can be chosen to either slightly degrade SNR or to slightly increase the DC offset and FS/2 spur. In addition, the FS/4 spur will also be increased slightly while in single channel mode. |
1 | ADC_DITH_AMP | R/W | 0x0 | 0 : Small dither for better SNR (default) |
0 | ADC_DITH_EN | R/W | 0x1 | Set this bit to enable ADC dither. Dither can improve spurious performance at the expense of slightly degraded SNR. The dither amplitude (ADC_DITH_AMP) can be used to further tradeoff SNR and spurious performance. |
LSB_CTRL is shown in Figure 7-60 and described in Table 7-97.
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LSB Control Bit Output (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIME_STAMP_EN | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | RESERVED | R/W | 0x0 | |
0 | TIME_STAMP_EN | R/W | 0x0 | When set, the timestamp signal is transmitted on the LSB of the output samples. The latency of the timestamp signal (through the entire chip) matches the latency of the analog ADC inputs. Also set SYNC_RECV_EN when using TIME_STAMP_EN. |
JESD_EN is shown in Figure 7-61 and described in Table 7-98.
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JESD204C Subsystem Enable (default: 0x01)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | JESD_EN | ||||||
R/W-0x0 | R/W-0x1 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | RESERVED | R/W | 0x0 | |
0 | JESD_EN | R/W | 0x1 | 0 : Disable JESD204C interface |
JMODE is shown in Figure 7-62 and described in Table 7-99.
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JESD204C Mode (default: 0x02)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RW |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | JMODE | RW | 0x02 | Specify the JESD204C Modes (including DDC decimation factor) Note 1: This register should only be changed when JESD_EN=0 and CAL_EN=0. Note 2: The MODE_LOCK register determines which modes are allowed. |
KM1 is shown in Figure 7-63 and described in Table 7-100.
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JESD204C K Parameter (default: 0x1F)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KM1 | |||||||
R/W-0x1F | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | KM1 | R/W | 0x1F | K is the number of frames per multiframe and this register must be programmed as K-1. Depending on the JMODE setting, there are constraints on the legal values of K (see KR). |
JSYNC_N is shown in Figure 7-64 and described in Table 7-101.
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JESD204C Manual Sync Request (default: 0x01)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | JSYNC_N | ||||||
R/W-0x0 | R/W-0x1 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | RESERVED | R/W | 0x0 | |
0 | JSYNC_N | R/W | 0x1 | Set this bit to 0 to request JESD204C synchronization (equivalent to the SYNC~ signal being asserted). For normal operation, leave this bit set to 1. |
JCTRL is shown in Figure 7-65 and described in Table 7-102.
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JESD204C Control (default: 0x03)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ALT_LANES | SYNC_SEL | SFORMAT | SCR | |||
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x1 | R/W-0x1 | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R/W | 0x0 | |
4 | ALT_LANES | R/W | 0x0 | 0 : Normal lane mapping (default). Link A uses lanes DA0 to DA3 and link B uses lanes DB0 to DB3. Other lanes are powered down. |
3:2 | SYNC_SEL | R/W | 0x0 | 0 : Use the SYNCSE input for SYNC~ function (default) |
1 | SFORMAT | R/W | 0x1 | Output sample format for JESD204C samples |
0 | SCR | R/W | 0x1 | 0 : 8B/10B Scrambler disabled (applies only to 8B/10B modes) |
JTEST is shown in Figure 7-66 and described in Table 7-103.
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JESD204C Test Control (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | JTEST | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R/W | 0x0 | |
4:0 | JTEST | R/W | 0x0 | 0 : Test mode disabled. Normal operation (default) |
DID is shown in Figure 7-67 and described in Table 7-104.
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JESD204C DID Parameter (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DID | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | DID | R/W | 0x0 | Specifies the DID (Device ID) value that is transmitted during the second multiframe of the JESD204B ILA. Link A will transmit DID, and link B will transmit DID+1. Bit 0 is ignored and always returns 0 (if you program an odd number, it will be decremented to an even number). |
FCHAR is shown in Figure 7-68 and described in Table 7-105.
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JESD204C Frame Character (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FCHAR | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | RESERVED | R/W | 0x0 | |
1:0 | FCHAR | R/W | 0x0 | Specify which comma character is used to denote end-of-frame. This character is transmitted opportunistically. This only applies to modes that use 8B/10B encoding. |
JESD_STATUS is shown in Figure 7-69 and described in Table 7-106.
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JESD204C / System Status Register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LINK_UP | SYNC_STATUS | REALIGNED | ALIGNED | PLL_LOCKED | RESERVED | |
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0x0 | |
6 | LINK_UP | R/W | 0x0 | When set, indicates that the JESD204C link is up. |
5 | SYNC_STATUS | R/W | 0x0 | Returns the state of the JESD204C SYNC~ signal. |
4 | REALIGNED | R/W | 0x0 | When high, indicates that the digital block clock, frame clock, or multiframe (LMFC) clock phase was realigned by SYSREF. Writing a 1 to this bit will clear it. |
3 | ALIGNED | R/W | 0x0 | When high, indicates that the multiframe (LMFC) clock phase has been established by SYSREF. The first SYSREF event after enabling the JESD204B encoder will set this bit. Writing a 1 to this bit will clear it. |
2 | PLL_LOCKED | R/W | 0x0 | When high, indicates that the serializer PLL is locked. |
1:0 | RESERVED | R/W | 0x0 |
PD_CH is shown in Figure 7-70 and described in Table 7-107.
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JESD204C Channel Power Down (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PD_BCH | PD_ACH | |||||
R/W-0x0 | R/W-0x0 | R/W-0x0 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | RESERVED | R/W | 0x0 | |
1 | PD_BCH | R/W | 0x0 | When set, the “B” ADC channel is powered down. The digital channels that are bound to the “B” ADC channel are also powered down (see DIG_BIND). |
0 | PD_ACH | R/W | 0x0 | When set, the “A” ADC channel is powered down. The digital channels that are bound to the “A” ADC channel are also powered down (see DIG_BIND). |
JEXTRA_A is shown in Figure 7-71 and described in Table 7-108.
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JESD204C Extra Lane Enable (Link A) (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXTRA_LANE_A | EXTRA_SER_A | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | EXTRA_LANE_A | R/W | 0x0 | Program these register bits to enable extra lanes (even if the selected JMODE does not require the lanes to be enabled). EXTRA_LANE_A(n) enables An (n=1 to 7). This register enables the link layer clocks for the affected lanes. To also enable the extra serializes set EXTRA_SER_A=1. |
0 | EXTRA_SER_A | R/W | 0x0 | 0 : Only the link layer clocks for extra lanes are enabled. |
JEXTRA_B is shown in Figure 7-72 and described in Table 7-109.
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JESD204C Extra Lane Enable (Link B) (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXTRA_LANE_B | EXTRA_SER_B | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | EXTRA_LANE_B | R/W | 0x0 | Program these register bits to enable extra lanes (even if the selected JMODE does not require the lanes to be enabled). EXTRA_LANE_B(n) enables Bn (n=1 to 7). This register enables the link layer clocks for the affected lanes. To also enable the extra serializes set EXTRA_SER_B=1. |
0 | EXTRA_SER_B | R/W | 0x0 | 0 : Only the link layer clocks for extra lanes are enabled. |
SHMODE is shown in Figure 7-73 and described in Table 7-110.
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JESD204C Sync Word Mode (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SHMODE | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | RESERVED | R/W | 0x0 | |
1:0 | SHMODE | R/W | 0x0 | Select the mode for the 64b/66b sync word (32 bits of data per multi-block). This only applies when JMODE is selecting a 64b/66b mode. |
DDC_CFG is shown in Figure 7-74 and described in Table 7-111.
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DDC Configuration (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BOOST | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | RESERVED | R/W | 0x0 | |
0 | BOOST | R/W | 0x0 | DDC gain control. |
OVR_T0 is shown in Figure 7-75 and described in Table 7-112.
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Over-range Threshold 0 (default: 0xF2)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVR_T0 | |||||||
R/W-0xF2 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | OVR_T0 | R/W | 0xF2 | This parameter defines the absolute sample level that causes control bit 0 to be set. Control bit 0 is attached to the DDC I output samples. The detection level in dBFS (peak) is 20log10(OVR_T0/256) (Default: 0xF2 = 242-> -0.5dBFS) |
OVR_T1 is shown in Figure 7-76 and described in Table 7-113.
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Over-range Threshold 1 (default: 0xAB)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVR_T1 | |||||||
R/W-0xAB | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | OVR_T1 | R/W | 0xAB | This parameter defines the absolute sample level that causes control bit 1 to be set. Control bit 1 is attached to the DDC Q output samples. The detection level in dBFS (peak) is 20log10(OVR_T1/256) (Default: 0xAB = 171 -> -3.5dBFS) |
OVR_CFG is shown in Figure 7-77 and described in Table 7-114.
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Over-range Enable / Hold Off (default: 0x07)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OVR_EN | OVR_N | |||||
R/W-0x0 | R/W-0x0 | R/W-0x7 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | RESERVED | R/W | 0x0 | |
3 | OVR_EN | R/W | 0x0 | Enables over-range status output pins when set high. The ORA0, ORA1, ORB0 and ORB1 outputs are held low when OVR_EN is set low. This register only affects the over-range output pins (ORxx). JESD204C modes that transmit over-range bits are not affected by this register. |
2:0 | OVR_N | R/W | 0x7 | Program this register to adjust the pulse extension for the ORA0/1 and ORB0/1 outputs. The minimum pulse duration of the over-range outputs is 8 * 2OVR_N DEVCLK cycles. Incrementing this field doubles the monitoring period. |
CMODE is shown in Figure 7-78 and described in Table 7-115.
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DDC NCO Configuration Preset Mode (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMODE | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | RESERVED | R/W | 0x0 | |
1:0 | CMODE | R/W | 0x0 | This register sets the selection mode for the NCO frequency used in the DDC block. The NCO frequency and phase for DDC A are set by the FREQAx and PHASEAx registers and the NCO frequency and phase for DDC B are set by the FREQBx and PHASEBx registers, where x is the configuration preset (0 through 3). In single channel mode, the NCO selection method for DDC A in dual channel mode is used to set the NCO for the single channel DDC. |
CSEL is shown in Figure 7-79 and described in Table 7-116.
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DDC NCO Configuration Preset Select (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CSELB | CSELA | |||||
R/W-0x0 | R/W-0x0 | R/W-0x0 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | RESERVED | R/W | 0x0 | |
3:2 | CSELB | R/W | 0x0 | When CMODE=0, this register is used to select the active NCO configuration preset for DDC B In single channel mode, this register is ignored and CSELA must be used instead. |
1:0 | CSELA | R/W | 0x0 | When CMODE=0, this register is used to select the active NCO configuration preset for DDC A Example: If CSELA=0, then FREQA0 and PHASEA0 are the active settings. If CSELA=1, then FREQA1 and PHASEA1 are the active settings. |
DIG_BIND is shown in Figure 7-80 and described in Table 7-117.
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Digital Channel Binding (default: 0x02)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DIG_BIND[1] | DIG_BIND[0] | |||||
R/W-0x0 | R/W-0x1 | R/W-0x0 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | RESERVED | R/W | 0x0 | |
1 | DIG_BIND[1] | R/W | 0x1 | Digital channel B input select: |
0 | DIG_BIND[0] | R/W | 0x0 | Digital channel A input select: |
NCO_RDIV is shown in Figure 7-81 and described in Table 7-118.
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NCO Reference Divisor (default: 0x0000)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NCO_RDIV | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCO_RDIV | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | NCO_RDIV | R/W | 0x0 | Sometimes the 32-bit NCO frequency word does not provide the desired frequency step size and can only approximate the desired frequency. This results in a frequency error. Use this register to eliminate the frequency error. |
NCO_SYNC is shown in Figure 7-82 and described in Table 7-119.
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NCO Synchronization (default: 0x02)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NCO_SYNC_ILA | NCO_SYNC_NEXT | |||||
R/W-0x0 | R/W-0x1 | R/W-0x0 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | RESERVED | R/W | 0x0 | |
1 | NCO_SYNC_ILA | R/W | 0x1 | When this bit is set, the NCO phase is initialized on the LMFC/LEMC boundary immediately after the rising edge of the SYNC~ signal (default). This feature works in 8B/10B and 64B/66B modes. This feature can be used to precisely align the NCO phase in several ADCs. In 64B/66B modes SYNC~ is only used for this purpose and does not affect the link operation. |
0 | NCO_SYNC_NEXT | R/W | 0x0 | After writing ‘0’ and then ‘1’ to this bit, the next SYSREF rising edge will initialize the NCO phase. Once the NCO phase has been initialized by SYSREF, the NCO will not re-initialize on future SYSREF edges unless ‘0’ and ‘1’ is written to this bit again. |
FREQA0 is shown in Figure 7-83 and described in Table 7-120.
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NCO Frequency (Channel A, Preset 0) (default: 0xC0000000)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FREQA0 | |||||||||||||||||||||||||||||||
R/W-0xC0000000 | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:0 | FREQA0 | R/W | 0xC0000000 | The following description applies to FREQA0 thru FREQA3 and FREQB0 thru FREQB3. |
PHASEA0 is shown in Figure 7-84 and described in Table 7-121.
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NCO Phase (Channel A, Preset 0) (default: 0x0000)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHASEA0 | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASEA0 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | PHASEA0 | R/W | 0x0 | NCO phase for configuration preset 0. This value is left justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is PHASEA0 * 2-16 * 2π. This register can be interpreted as signed or unsigned. |
FREQA1 is shown in Figure 7-85 and described in Table 7-122.
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NCO Frequency (Channel A, Preset 1) (default: 0xC0000000)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FREQA1 | |||||||||||||||||||||||||||||||
R/W-0xC0000000 | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:0 | FREQA1 | R/W | 0xC0000000 | NCO frequency for channel A, NCO preset 1 |
PHASEA1 is shown in Figure 7-86 and described in Table 7-123.
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NCO Phase (Channel A, Preset 1) (default: 0x0000)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHASEA1 | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASEA1 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | PHASEA1 | R/W | 0x0 | NCO phase for channel A, preset 1 |
FREQA2 is shown in Figure 7-87 and described in Table 7-124.
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NCO Frequency (Channel A, Preset 2) (default: 0xC0000000)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FREQA2 | |||||||||||||||||||||||||||||||
R/W-0xC0000000 | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:0 | FREQA2 | R/W | 0xC0000000 | NCO frequency for channel A, NCO preset 2 |
PHASEA2 is shown in Figure 7-88 and described in Table 7-125.
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NCO Phase (Channel A, Preset 2) (default: 0x0000)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHASEA2 | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASEA2 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | PHASEA2 | R/W | 0x0 | NCO phase for channel A, preset 2 |
FREQA3 is shown in Figure 7-89 and described in Table 7-126.
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NCO Frequency (Channel A, Preset 3) (default: 0xC0000000)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FREQA3 | |||||||||||||||||||||||||||||||
R/W-0xC0000000 | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:0 | FREQA3 | R/W | 0xC0000000 | NCO frequency for channel A, NCO preset 3 |
PHASEA3 is shown in Figure 7-90 and described in Table 7-127.
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NCO Phase (Channel A, Preset 3) (default: 0x0000)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHASEA3 | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASEA3 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | PHASEA3 | R/W | 0x0 | NCO phase for channel A, preset 3 |
FREQB0 is shown in Figure 7-91 and described in Table 7-128.
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NCO Frequency (Channel B, Preset 0) (default: 0xC0000000)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FREQB0 | |||||||||||||||||||||||||||||||
R/W-0xC0000000 | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:0 | FREQB0 | R/W | 0xC0000000 | NCO frequency for channel B, NCO preset 0. |
PHASEB0 is shown in Figure 7-92 and described in Table 7-129.
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NCO Phase (Channel B, Preset 0) (default: 0x0000)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHASEB0 | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASEB0 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | PHASEB0 | R/W | 0x0 | NCO phase for channel B, preset 0 |
FREQB1 is shown in Figure 7-93 and described in Table 7-130.
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NCO Frequency (Channel B, Preset 1) (default: 0xC0000000)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FREQB1 | |||||||||||||||||||||||||||||||
R/W-0xC0000000 | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:0 | FREQB1 | R/W | 0xC0000000 | NCO frequency for channel B, NCO preset 1 |
PHASEB1 is shown in Figure 7-94 and described in Table 7-131.
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NCO Phase (Channel B, Preset 1) (default: 0x0000)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHASEB1 | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASEB1 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | PHASEB1 | R/W | 0x0 | NCO phase for channel B, preset 1 |
FREQB2 is shown in Figure 7-95 and described in Table 7-132.
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NCO Frequency (Channel B, Preset 2) (default: 0xC0000000)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FREQB2 | |||||||||||||||||||||||||||||||
R/W-0xC0000000 | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:0 | FREQB2 | R/W | 0xC0000000 | NCO frequency for channel B, NCO preset 2 |
PHASEB2 is shown in Figure 7-96 and described in Table 7-133.
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NCO Phase (Channel B, Preset 2) (default: 0x0000)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHASEB2 | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASEB2 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | PHASEB2 | R/W | 0x0 | NCO phase for channel B, preset 2 |
FREQB3 is shown in Figure 7-97 and described in Table 7-134.
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NCO Frequency (Channel B, Preset 3) (default: 0xC0000000)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FREQB3 | |||||||||||||||||||||||||||||||
R/W-0xC0000000 | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:0 | FREQB3 | R/W | 0xC0000000 | NCO frequency for channel B, NCO preset 3 |
PHASEB3 is shown in Figure 7-98 and described in Table 7-135.
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NCO Phase (Channel B, Preset 3) (default: 0x0000)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHASEB3 | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASEB3 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | PHASEB3 | R/W | 0x0 | NCO phase for channel B, preset 3 |
INIT_STATUS is shown in Figure 7-99 and described in Table 7-136.
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Chip Spin Identifier (default: See description, read-only)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INIT_STATUS | ||||||
R-undefined | R-undefined |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | RESERVED | R | undefined | RESERVED |
0 | INIT_DONE | R | undefined | Returns 1 when the initialization logic has finished initializing the device. This indicates that it is now safe to proceed with startup. No SPI transactions should be performed before INIT_DONE returns 1(except SOFT_RESET). |
SPIN_ID is shown in Figure 7-100 and described in Table 7-137.
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Chip Spin Identifier (default: See description, read-only)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPIN_ID | ||||||
R/W-0x0 | R/W-0x00 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R/W | 0x0 | |
4:0 | SPIN_ID | R/W | 0x0 | Spin identification value: 0: ADC12DJ5200RF 1: ADC12DJ5200-SP 2 : ADC12DJ4000RF 7: ADC12DJ5200-EP 10: ADC08DJ5200RF |
TESTBUS is shown in Figure 7-101 and described in Table 7-138.
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TESTBUS Register (default: 0x0)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EN_VD11_NOISE_SUPPR | EN_VS11_NOISE_SUPPR | RESERVED | ||||
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | RESERVED | R/W | 0x0 | RESERVED |
5 | EN_VD11_NOISE_SUPPR | R/W | 0x0 | When set, noise on VD11 is suppressed. It is recommended to have this set, as it reduces noise coupling from the digital circuits to analog clock, at the expense of a small increase in power. |
4 | EN_VS11_NOISE_SUPPR | R/W | When set, noise on VS11 is suppressed. It is recommended to have this set, as it reduces noise coupling from the digital circuits to analog clock, at the expense of a small increase in power. | |
3:0 | RESERVED | R/W | R/W | RESERVED |
SRC_EN is shown in Figure 7-102 and described in Table 7-139.
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SYSREF Calibration Enable (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRC_EN | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | RESERVED | R/W | 0x0 | |
0 | SRC_EN | R/W | 0x0 | 0: SYSREF Calibration Disabled. Use the TAD register to manually control the tad[16:0] output and adjust the DEVCLK delay. (default) |
SRC_CFG is shown in Figure 7-103 and described in Table 7-140.
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SYSREF Calibration Configuration (default: 0x05)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRC_AVG | SRC_HDUR | |||||
R/W-0x0 | R/W-0x1 | R/W-0x1 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | RESERVED | R/W | 0x0 | |
3:2 | SRC_AVG | R/W | 0x1 | Specifies the amount of averaging used for SYSREF Calibration. Larger values will increase calibration time and reduce the variance of the calibrated value. |
1:0 | SRC_HDUR | R/W | 0x1 | Specifies the duration of each high-speed accumulation for SYSREF Calibration. If the SYSREF period exceeds the supported value, calibration will fail. Larger values will increase calibration time and support longer SYSREF periods. For a given SYSREF period, larger values will also reduce the variance of the calibrated value. |
SRC_STATUS is shown in Figure 7-104 and described in Table 7-141.
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SYSREF Calibration Status (read-only, default: undefined)
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | SRC_DONE | SRC_TAD | |||||
R/W-0x0 | R/W-0x0 | R/W-0x0 | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SRC_TAD | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SRC_TAD | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
23:18 | RESERVED | R/W | 0x0 | |
17 | SRC_DONE | R/W | 0x0 | This bit returns ‘1’ when SRC_EN=1 and SYSREF Calibration has been completed. |
16:0 | SRC_TAD | R/W | 0x0 | This field returns the value for TAD[16:0] computed by SYSREF Calibration. It is only valid if SRC_DONE=1. |
TAD is shown in Figure 7-105 and described in Table 7-142.
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DEVCLK Timing Adjust (default: 0x00)
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TAD_INV | ||||||
R/W-0x0 | R/W-0x0 | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TAD_COARSE | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TAD_FINE | |||||||
R-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
23:17 | RESERVED | R/W | 0x0 | |
16 | TAD_INV | R/W | 0x0 | Inverts the sampling clock when set. |
15:8 | TAD_COARSE | R/W | 0x0 | This register controls the coarse resolution of the sampling aperture delay adjustment when SRC_EN=0. Use this register to manually control the DEVCLK aperture delay when SYSREF Calibration is disabled. If ADC calibration or JESD204B is running, it is recommended that you gradually increase or decrease this value (1 code at a time) to avoid clock glitches. Refer to Switching Characteristics for TAD_COARSE resolution. |
7:0 | TAD_FINE | R/W | 0x0 | This register controls the fine resolution of the sampling aperture delay adjustment when SRC_EN=0. Use this register to manually control the DEVCLK aperture delay when SYSREF Calibration is disabled. Refer to Switching Characteristics for TAD_FINE resolution. TAD_FINE may be changed to any value at any time (its adjustment is too fine to cause clock glitches). |
TAD_RAMP is shown in Figure 7-106 and described in Table 7-143.
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DEVCLK Timing Adjust Ramp Control (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TAD_RAMP_RATE | TAD_RAMP_EN | |||||
R/W-0x0 | R/W-0x0 | R/W-0x0 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | RESERVED | R/W | 0x0 | |
1 | TAD_RAMP_RATE | R/W | 0x0 | Specifies the ramp rate for TAD_COARSE when the TAD_COARSE register is written while TAD_RAMP_EN=1. |
0 | TAD_RAMP_EN | R/W | 0x0 | TAD ramp enable. Set this bit if you want the coarse TAD adjustment (TAD_COARSE) to ramp up or down instead of changing abruptly. |
ALARM is shown in Figure 7-107 and described in Table 7-144.
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Alarm Interrupt (read-only)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ALARM | ||||||
R-0x0 | R-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | RESERVED | R | 0x0 | |
0 | ALARM | R | 0x0 | This bit returns a ‘1’ whenever any alarm occurs that is unmasked in the ALM_STATUS register. Use ALM_MASK to mask (disable) individual alarms. CAL_STATUS_SEL can be used to drive the ALARM bit onto the CALSTAT output pin to provide a hardware alarm interrupt signal. |
ALM_STATUS is shown in Figure 7-108 and described in Table 7-145.
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Alarm Status (default: 0x3F, write to clear)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FIFO_ALM | PLL_ALM | LINK_ALM | REALIGNED_ALM | NCO_ALM | CLK_ALM | |
R/W-0x0 | R/W-0x1 | R/W-0x1 | R/W-0x1 | R/W-0x1 | R/W-0x1 | R/W-0x1 | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | RESERVED | R/W | 0x0 | |
5 | FIFO_ALM | R/W | 0x1 | FIFO overflow/underflow alarm: This bit is set whenever an active JESD204C lane FIFO experiences an underflow or overflow condition. Write a ‘1’ to clear this bit. To inspect which lane generated the alarm, read FIFO_LANE_ALM. |
4 | PLL_ALM | R/W | 0x1 | PLL Lock Lost Alarm: This bit is set whenever the PLL is not locked. Write a ‘1’ to clear this bit. |
3 | LINK_ALM | R/W | 0x1 | Link Alarm: This bit is set whenever the JESD204C link is enabled, but is not in the data encoder state (for 8B/10B modes). In 64B/66B modes, there is no data encoder state, so this alarm will be set when the link first starts up, and will also be set if any event causes a FIFO/serializer realignment. Write a ‘1’ to clear this bit. |
2 | REALIGNED_ALM | R/W | 0x1 | Realigned Alarm: This bit is set whenever SYSREF causes the internal clocks (including the LMFC/LEMC) to be realigned. Write a ‘1’ to clear this bit. |
1 | NCO_ALM | R/W | 0x1 | NCO Alarm: This bit can be used to detect an upset to the NCO phase. This bit is set when any of the following occur: - The NCOs are disabled (JESD_EN=0). - The NCOs are synchronized (intentionally or unintentionally) - Any phase accumulators in channel A do not match channel B. Write a ‘1’ to clear this bit. Refer to the alarm section for the proper usage of this register. |
0 | CLK_ALM | R/W | 0x1 | Clock Alarm: This bit can be used to detect an upset to the internal DDC/JESD204C clocks. This bit is set whenever the internal clock dividers for the A and B channels do not match. Write a ‘1’ to clear this bit. Refer to the alarm section for the proper usage of this register. Note: After power-on reset or soft-reset, all alarm bits are set to ‘1.’ Note: When JESD_EN=0, all alarms (except CLK_ALM) are undefined. It is recommended that the user clears the alarms after setting JESD_EN=1. |
ALM_MASK is shown in Figure 7-109 and described in Table 7-146.
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Alarm Mask Register (default: 0x3F)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MASK_FIFO_ALM | MASK_PLL_ALM | MASK_LINK_ALM | MASK_REALIGNED_ALM | MASK_NCO_ALM | MASK_CLK_ALM | |
R/W-0x0 | R/W-0x1 | R/W-0x1 | R/W-0x1 | R/W-0x1 | R/W-0x1 | R/W-0x1 | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | RESERVED | R/W | 0x0 | |
5 | MASK_FIFO_ALM | R/W | 0x1 | When set, FIFO_ALM is masked and will not impact the ALARM register bit. |
4 | MASK_PLL_ALM | R/W | 0x1 | When set, PLL_ALM is masked and will not impact the ALARM register bit. |
3 | MASK_LINK_ALM | R/W | 0x1 | When set, LINK_ALM is masked and will not impact the ALARM register bit. |
2 | MASK_REALIGNED_ALM | R/W | 0x1 | When set, REALIGNED_ALM is masked and will not impact the ALARM register bit. |
1 | MASK_NCO_ALM | R/W | 0x1 | When set, NCO_ALM is masked and will not impact the ALARM register bit. |
0 | MASK_CLK_ALM | R/W | 0x1 | When set, CLK_ALM is masked and will not impact the ALARM register bit. |
FIFO_LANE_ALM is shown in Figure 7-110 and described in Table 7-147.
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FIFO Overflow/Underflow Alarm (default: 0xFFFF)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FIFO_LANE_ALM | |||||||
R/W-0xFFFF | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFO_LANE_ALM | |||||||
R/W-0xFFFF | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | FIFO_LANE_ALM | R/W | 0xFFFF | FIFO_LANE_ALM[i] is set if the FIFO for lane i experiences overflow or underflow. Use this register to determine which lane(s) generated an alarm. Writing a ‘1’ to any bit in this register will clear the alarm (the alarm may immediately trip again if the overflow/underflow condition persists). Writing a ‘1’ to the FIFO_ALM bit in the ALM_STATUS register will clear all bits of this register. |
TADJ_A is shown in Figure 7-111 and described in Table 7-148.
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Timing Adjust for A-ADC operating in Dual Channel Mode (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TADJ_A | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | TADJ_A | R/W | 0x0 | This register (and other TADJ* registers that follow it) are used to adjust the sampling instant of each ADC core. Different TADJ registers apply to different ADCs under different modes. The default values for all TADJ* registers are factory programmed values. The factory trimmed values can be read out and adjusted as required. |
TADJ_B is shown in Figure 7-112 and described in Table 7-149.
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Timing Adjust for B-ADC operating in Dual Channel Mode (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TADJ_B | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | TADJ_B | R/W | 0x0 | See TADJ_A register for description. Adjusts timing of B-ADC in dual channel mode with foreground calibration enabled. |
TADJ_A_FG90_VINA is shown in Figure 7-113 and described in Table 7-150.
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Timing Adjust for A-ADC operating in Single Channel Mode and sampling INA± (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TADJ_A_FG90_VINA | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | TADJ_A_FG90_VINA | R/W | 0x0 | See TADJ_A register for description. Adjusts timing of A-ADC in single channel mode with foreground calibration enabled and sampling INA±. |
TADJ_B_FG0_VINA is shown in Figure 7-114 and described in Table 7-151.
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Timing Adjust for B-ADC operating in Single Channel Mode and sampling INA± (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TADJ_B_FG0_VINA | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | TADJ_B_FG0_VINA | R/W | 0x0 | See TADJ_A register for description. Adjusts timing of B-ADC in single channel mode with foreground calibration enabled and sampling INA±. |
TADJ_A_FG90_VINB is shown in Figure 7-115 and described in Table 7-152.
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Timing Adjust for A-ADC operating in Single Channel Mode and sampling INB± (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TADJ_A_FG90_VINB | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | TADJ_A_FG90_VINB | R/W | 0x0 | See TADJ_A register for description. Adjusts timing of A-ADC in single channel mode with foreground calibration enabled and sampling INB±. |
TADJ_B_FG0_VINB is shown in Figure 7-116 and described in Table 7-153.
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Timing Adjust for B-ADC operating in Single Channel Mode and sampling INB± (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TADJ_B_FG0_VINB | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | TADJ_B_FG0_VINB | R/W | 0x0 | See TADJ_A register for description. Adjusts timing of B-ADC in single channel mode with foreground calibration enabled and sampling INB±. |
OADJ_A_FG0_VINA is shown in Figure 7-117 and described in Table 7-154.
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Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INA± (default from Fuse ROM)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | OADJ_A_FG0_VINA | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OADJ_A_FG0_VINA | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | OADJ_A_FG0_VINA | R/W | 0x0 | Offset adjustment value applied to A-ADC when it samples INA± in dual channel mode and foreground calibration is enabled. |
OADJ_A_FG0_VINB is shown in Figure 7-118 and described in Table 7-155.
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Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INB± (default from Fuse ROM)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | OADJ_A_FG_VINB | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OADJ_A_FG_VINB | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | OADJ_A_FG_VINB | R/W | 0x0 | Offset adjustment value applied to A-ADC when it samples INB± in dual channel mode and foreground calibration is enabled. |
OADJ_A_FG90_VINA is shown in Figure 7-119 and described in Table 7-156.
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Offset Adjustment for A-ADC operating in Single Channel Mode sampling INA± (default from Fuse ROM)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | OADJ_A_FG90_VINA | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OADJ_A_FG90_VINA | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | OADJ_A_FG90_VINA | R/W | 0x0 | Offset adjustment value applied to A-ADC when it samples INA± in single channel mode and foreground calibration is enabled. |
OADJ_A_FG90_VINB is shown in Figure 7-120 and described in Table 7-157.
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Offset Adjustment for A-ADC operating in Single Channel Mode sampling INB± (default from Fuse ROM)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | OADJ_A_FG90_VINB | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OADJ_A_FG90_VINB | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | OADJ_A_FG90_VINB | R/W | 0x0 | Offset adjustment value applied to A-ADC when it samples INB± using 90° clock phase and foreground calibration is enabled. |
OADJ_B_FG0_VINA is shown in Figure 7-121 and described in Table 7-158.
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Offset Adjustment for B-ADC sampling INA± (default from Fuse ROM)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | OADJ_B_FG0_VINA | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OADJ_B_FG0_VINA | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | OADJ_B_FG0_VINA | R/W | 0x0 | Offset adjustment value applied to B-ADC when it samples INA± and foreground calibration is enabled. Applies to both dual channel mode and single channel mode. |
OADJ_B_FG0_VINB is shown in Figure 7-122 and described in Table 7-159.
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Offset Adjustment for B-ADC sampling INB± (default from Fuse ROM)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | OADJ_B_FG0_VINB | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OADJ_B_FG0_VINB | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | OADJ_B_FG0_VINB | R/W | 0x0 | Offset adjustment value applied to B-ADC when it samples INB± and foreground calibration is enabled. Applies to both dual channel mode and single channel mode. |
GAIN_A0_FGDUAL is shown in Figure 7-123 and described in Table 7-160.
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Fine Gain Adjust for ADC A Bank 0 in Dual Channel Mode (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GAIN_A0_FGDUAL | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R/W | 0x0 | |
4:0 | GAIN_A0_FGDUAL | R/W | 0x0 | Fine gain adjustment for ADC A bank 0. |
GAIN_A1_FGDUAL is shown in Figure 7-124 and described in Table 7-161.
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Fine Gain Adjust for ADC A Bank 1 in Dual Channel Mode (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GAIN_A1_FGDUAL | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R/W | 0x0 | |
4:0 | GAIN_A1_FGDUAL | R/W | 0x0 | Fine gain adjustment for ADC A bank 1. |
GAIN_B0_FGDUAL is shown in Figure 7-125 and described in Table 7-162.
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Fine Gain Adjust for ADC B Bank 0 in Dual Channel Mode (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GAIN_A0_FGDUAL | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R/W | 0x0 | |
4:0 | GAIN_A0_FGDUAL | R/W | 0x0 | Fine gain adjustment for ADC B bank 0. |
GAIN_B1_FGDUAL is shown in Figure 7-126 and described in Table 7-163.
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Fine Gain Adjust for ADC B Bank 1 in Dual Channel Mode (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GAIN_B1_FGDUAL | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R/W | 0x0 | |
4:0 | GAIN_B1_FGDUAL | R/W | 0x0 | Fine gain adjustment for ADC B bank 1. |
GAIN_A0_FGDES is shown in Figure 7-127 and described in Table 7-164.
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Fine Gain Adjust for ADC A Bank 0 in Single Channel Mode (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GAIN_A0_FGDUAL | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R/W | 0x0 | |
4:0 | GAIN_A0_FGDUAL | R/W | 0x0 | Fine gain adjustment for ADC A bank 0. |
GAIN_A1_FGDES is shown in Figure 7-128 and described in Table 7-165.
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Fine Gain Adjust for ADC A Bank 1 in Single Channel Mode (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GAIN_A1_FGDUAL | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R/W | 0x0 | |
4:0 | GAIN_A1_FGDUAL | R/W | 0x0 | Fine gain adjustment for ADC A bank 1. |
GAIN_B0_FGDES is shown in Figure 7-129 and described in Table 7-166.
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Fine Gain Adjust for ADC B Bank 0 in Single Channel Mode (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GAIN_A0_FGDUAL | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R/W | 0x0 | |
4:0 | GAIN_A0_FGDUAL | R/W | 0x0 | Fine gain adjustment for ADC B bank 0. |
GAIN_B1_FGDES is shown in Figure 7-130 and described in Table 7-167.
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Fine Gain Adjust for ADC B Bank 1 in Single Channel Mode (default from Fuse ROM)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GAIN_B1_FGDUAL | ||||||
R/W-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R/W | 0x0 | |
4:0 | GAIN_B1_FGDUAL | R/W | 0x0 | Fine gain adjustment for ADC B bank 1. |
PFIR_CFG is shown in Figure 7-131 and described in Table 7-168.
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Programmable FIR Mode (default: 0x00)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PFIR_SHARE | PFIR_MERGE | PFIR_SCW | PFIR_MODE | |||
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0x0 | |
6 | PFIR_SHARE | R/W | 0x0 | When set, the PFIR on the B channel uses the same coefficients as the PFIR on the A channel. When PFIR_SHARE=0, the B channel filter uses its own set of coefficients (unique from channel A). See Programmable FIR Filter (PFIR) section for usage details. |
5 | PFIR_MERGE | R/W | 0x0 | When set, the PFIR filters are merged into a single logical filter. This mode processes ADC data samples as if they belong to a single sample stream. Set PFIR_MERGE=1 whenever the ADC is setup in Single Channel Mode. |
4:2 | PFIR_SCW | R/W | 0x0 | Side coefficient weight for PFIR. This field determines the weight of the coefficients (except for the center coefficient). Increasing the coefficient weight increases the range of the coefficients at the expense of reduced precision. The LSB weight is 2PFIR_SCW-16, where PFIR_SCW weight can be programmed from 0 to 6. The default is 0 which provides an LSB weight of 2-16. |
1:0 | PFIR_MODE | R/W | 0x0 | 0 : PFIR block is disabled (default) |
PFIR_A0 is shown in Figure 7-132 and described in Table 7-169.
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PFIR Coefficient A0
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFIR_A0 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_A0 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | PFIR_A0 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the first tap for the ADC A programmable FIR filter in Dual Channel Mode or the first tap for the programmable FIR filter in Single Channel Mode. |
PFIR_A1 is shown in Figure 7-133 and described in Table 7-170.
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PFIR Coefficient A1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFIR_A1 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_A1 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | PFIR_A1 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the second tap for the ADC A programmable FIR filter in Dual Channel Mode or the second tap for the programmable FIR filter in Single Channel Mode. |
PFIR_A2 is shown in Figure 7-134 and described in Table 7-171.
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PFIR Coefficient A2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFIR_A2 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_A2 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | PFIR_A2 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the third tap for the ADC A programmable FIR filter in Dual Channel Mode or the third tap for the programmable FIR filter in Single Channel Mode. |
PFIR_A3 is shown in Figure 7-135 and described in Table 7-172.
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PFIR Coefficient A3
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFIR_A3 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_A3 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | PFIR_A3 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the fourth tap for the ADC A programmable FIR filter in Dual Channel Mode or the fourth tap for the programmable FIR filter in Single Channel Mode. |
PFIR_A4 is shown in Figure 7-136 and described in Table 7-173.
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PFIR Coefficient A4
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PFIR_A4 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PFIR_A4 | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_A4 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
23:18 | RESERVED | R/W | 0x0 | |
17:0 | PFIR_A4 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the fifth tap for the ADC A programmable FIR filter in Dual Channel Mode or the fifth tap for the programmable FIR filter in Single Channel Mode. This is the center tap of the 9-tap filter and therefore has a resolution of 18-bits. |
PFIR_A5 is shown in Figure 7-137 and described in Table 7-174.
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PFIR Coefficient A5
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFIR_A5 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_A5 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | PFIR_A5 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the sixth tap for the ADC A programmable FIR filter in Dual Channel Mode or the sixth tap for the programmable FIR filter in Single Channel Mode. |
PFIR_A6 is shown in Figure 7-138 and described in Table 7-175.
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PFIR Coefficient A6
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFIR_A6 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_A6 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | PFIR_A6 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the seventh tap for the ADC A programmable FIR filter in Dual Channel Mode or the seventh tap for the programmable FIR filter in Single Channel Mode. |
PFIR_A7 is shown in Figure 7-139 and described in Table 7-176.
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PFIR Coefficient A7
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFIR_A7 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_A7 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | PFIR_A7 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the eighth tap for the ADC A programmable FIR filter in Dual Channel Mode or the eighth tap for the programmable FIR filter in Single Channel Mode. |
PFIR_A8 is shown in Figure 7-140 and described in Table 7-177.
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PFIR Coefficient A8
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFIR_A8 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_A8 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | PFIR_A8 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the ninth tap for the ADC A programmable FIR filter in Dual Channel Mode or the ninth tap for the programmable FIR filter in Single Channel Mode. |
PFIR_B0 is shown in Figure 7-141 and described in Table 7-178.
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PFIR Coefficient B0
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFIR_B0 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_B0 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | PFIR_B0 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the first tap for the ADC B programmable FIR filter in Dual Channel Mode. |
PFIR_B1 is shown in Figure 7-142 and described in Table 7-179.
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PFIR Coefficient B1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFIR_B1 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_B1 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | PFIR_B1 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the second tap for the ADC B programmable FIR filter in Dual Channel Mode. |
PFIR_B2 is shown in Figure 7-143 and described in Table 7-180.
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PFIR Coefficient B2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFIR_B2 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_B2 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | PFIR_B2 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the third tap for the ADC B programmable FIR filter in Dual Channel Mode. |
PFIR_B3 is shown in Figure 7-144 and described in Table 7-181.
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PFIR Coefficient B3
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFIR_B3 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_B3 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | PFIR_B3 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the fourth tap for the ADC B programmable FIR filter in Dual Channel Mode. |
PFIR_B4 is shown in Figure 7-145 and described in Table 7-182.
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PFIR Coefficient B4
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PFIR_B4 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PFIR_B4 | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_B4 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
23:18 | RESERVED | R/W | 0x0 | |
17:0 | PFIR_B4 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the fifth tap for the ADC B programmable FIR filter in Dual Channel Mode. This is the center tap of the 9-tap filter and therefore has a resolution of 18-bits. |
PFIR_B5 is shown in Figure 7-146 and described in Table 7-183.
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PFIR Coefficient B5
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFIR_B5 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_B5 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | PFIR_B5 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the sixth tap for the ADC B programmable FIR filter in Dual Channel Mode. |
PFIR_B6 is shown in Figure 7-147 and described in Table 7-184.
Return to the Summary Table.
PFIR Coefficient B6
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFIR_B6 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_B6 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | PFIR_B6 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the seventh tap for the ADC B programmable FIR filter in Dual Channel Mode. |
PFIR_B7 is shown in Figure 7-148 and described in Table 7-185.
Return to the Summary Table.
PFIR Coefficient B7
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFIR_B7 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_B7 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | PFIR_B7 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the eighth tap for the ADC B programmable FIR filter in Dual Channel Mode. |
PFIR_B8 is shown in Figure 7-149 and described in Table 7-186.
Return to the Summary Table.
PFIR Coefficient B8
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFIR_B8 | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PFIR_B8 | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0x0 | |
11:0 | PFIR_B8 | R(1)/W | 0x0 | Signed, 2’s complement coefficient for the PFIR filter. This is the ninth tap for the ADC B programmable FIR filter in Dual Channel Mode. |