SNVSA18C April   2014  – August 2014 ADC16DX370

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Converter Performance Characteristics
    6. 6.6  Power Supply Electrical Characteristics
    7. 6.7  Analog Interface Electrical Characteristics
    8. 6.8  CLKIN, SYSREF, SYNCb Interface Electrical Characteristics
    9. 6.9  Serial Data Output Interface Electrical Characteristics
    10. 6.10 Digital Input Electrical Interface Characteristics
    11. 6.11 Timing Requirements
    12. 6.12 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Over-Range Functional Characteristics
    2. 7.2 Input Clock Divider and Clock Phase Adjustment Functional Characteristics
    3. 7.3 JESD204B Interface Functional Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Amplitude and Phase Imbalance Correction of Differential Analog Input
      2. 8.3.2  DC Offset Correction
      3. 8.3.3  Over-Range Detection
      4. 8.3.4  Input Clock Divider
      5. 8.3.5  SYSREF Offset Feature and Detection Gate
      6. 8.3.6  Sampling Instant Phase Adjustment
      7. 8.3.7  Serial Differential Output Drivers
        1. 8.3.7.1 De-Emphasis Equalization
      8. 8.3.8  ADC Core Calibration
      9. 8.3.9  Data Format
      10. 8.3.10 JESD204B Supported Features
      11. 8.3.11 Transport Layer Configuration
        1. 8.3.11.1 Lane Configuration
        2. 8.3.11.2 Frame Format
        3. 8.3.11.3 ILA Information
      12. 8.3.12 Test Pattern Sequences
      13. 8.3.13 JESD204B Link Initialization
      14. 8.3.14 SPI
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down and Sleep Modes
    5. 8.5 Register Map
      1. 8.5.1 Register Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input Considerations
        1. 9.1.1.1 Differential Analog Inputs and Full Scale Range
        2. 9.1.1.2 Analog Input Network Model
        3. 9.1.1.3 Input Bandwidth
        4. 9.1.1.4 Driving the Analog Input
        5. 9.1.1.5 Clipping and Over-Range
      2. 9.1.2 CLKIN, SYSREF, and SYNCb Input Considerations
        1. 9.1.2.1 Driving the CLKIN+ and CLKIN- Input
        2. 9.1.2.2 Clock Noise and Edge Rate
        3. 9.1.2.3 Driving the SYSREF Input
        4. 9.1.2.4 SYSREF Signaling
        5. 9.1.2.5 SYSREF Timing
        6. 9.1.2.6 Effectively Using the SYSREF Offset and Detection Gate Features
        7. 9.1.2.7 Driving the SYNCb Input
      3. 9.1.3 Output Serial Interface Considerations
        1. 9.1.3.1 Output Serial-Lane Interface
        2. 9.1.3.2 Voltage Swing and De-Emphasis Optimization
        3. 9.1.3.3 Minimizing EMI
      4. 9.1.4 JESD204B System Considerations
        1. 9.1.4.1 Frame and LMFC Clock Alignment Procedure
        2. 9.1.4.2 Link Interruption
        3. 9.1.4.3 Synchronization Requests and SYNCb Alignment in Multi-Device Systems
        4. 9.1.4.4 Clock Configuration Examples
        5. 9.1.4.5 Configuring the JESD204B Receiver
      5. 9.1.5 SPI
    2. 9.2 Typical Application
      1. 9.2.1 High-IF Sampling Receiver
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Design Procedure
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Design
    2. 10.2 Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Specification Definitions
      2. 12.1.2 JESD204B Definitions
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

WQFN PACKAGE
56 PINS
(TOP VIEW)
ADC16DX370 Pinout.gif

Pin Functions

PIN TYPE OR DIAGRAM DESCRIPTION
NAME NUMBER
AGND 3, 6, 9, 12, 16, 19, 22, 31, 40, 49, 52, 55 Analog ground Analog ground
Must be connected to a solid ground reference plane under the device.
BP2.5 41 Bypass pins Capacitive bypassing pin for internally regulated 2.5-V supply
This pin must be decoupled to AGND with a 0.1-μF and a 10-µF capacitor located close to the pin.
CLKIN+, CLKIN– 17, 18
ADC16DX370 pin_CLKIN.gif
Differential device clock input pins
Each pin is internally terminated to a DC bias with a 50-Ω resistor for a 100-Ω total internal differential termination. AC coupling is required for coupling the clock input to these pins if the clock driver cannot meet the common-mode requirements. Sampling occurs on the rising edge of the differential signal (CLKIN+) − (CLKIN–).
CSB 54
ADC16DX370 pin_SDI_CSb_SCLK.gif
SPI chip select pin
When this signal is asserted, SCLK is used to clock the input serial data on the SDI pin or output serial data on the SDO pin. When this signal is de-asserted, the SDO pin is high impedance and the input data is ignored. Active low. A 10 kΩ pull-up resistor to the VA1.8 supply is recommended to prevent undesired activation of the SPI bus. Compatible with 1.2- to 3.0-V CMOS logic levels.
DGND 25, 46 Digital ground Digital ground
Must be connected to the same solid ground reference plane under the device to which AGND connects. Bypass capacitors connected to the VD1.2 pins must be connected to ground as close to this DGND pins as possible.
OVRA, OVRB 44, 43
ADC16DX370 pin_OVRA.gif
Over-range detection outputs
These pins output the channel A and channel B over-range signals as 1.8-V CMOS logic level outputs.
SA0+, SA0–, SA1+, SA1– 38, 39, 36, 37
ADC16DX370 pin_S0.gif
Differential high speed serial data lane pins for channel A
These pins must be AC coupled to the receiving device. The differential trace routing from these pins must maintain a 100-Ω characteristic impedance. In single-lane mode, SA0+ or SAO– is used to transfer data and SA1+ or SA1– is undefined and may be left floating.
SB0+, SB0–, SB1+, SB1– 32, 33, 34, 35 Differential high speed serial data lane pins for channel B. These pins must be AC coupled to the receiving device. The differential trace routing from these pins must maintain a 100-Ω characteristic impedance. In single-lane mode, SB0+ or SB0– is used to transfer data and SB1+ and SB1– is undefined and may be left floating.
SCLK 53
ADC16DX370 pin_SDI_CSb_SCLK.gif
SPI serial clock pin
Serial data is shifted into and out of the device synchronous with this clock signal. Compatible with 1.2- to 3.0-V CMOS logic levels.
SDI 47 SPI data input pin
Serial data is shifted into the device on this pin while the CSB signal is asserted. Compatible with 1.2- to 3.0-V CMOS logic levels.
SDO 48
ADC16DX370 pin_SDO.gif
SPI data output pin
Serial data is shifted out of the device on this pin during a read command while CSB is asserted. The output logic level is configurable as 1.2, 1.8, 2.5, or 3.0 V. The output level must be configured after power up and before performing a read command. See the Register Descriptions for configuration details.
SYNCb+, SYNCb– 27, 28
ADC16DX370 pin_SYNC.gif
Differential SYNCb signal input pins
DC coupling is required for coupling the SYNCb signal to these pins. Each pin is internally terminated to the DC bias with a large resistor. An internal 100-Ω differential termination is provided therefore an external termination is not required. Additional resistive components in the input structure give the SYNCb input a wide input common-mode range. The SYNCb signal is active low and therefore asserted when the voltage at SYNCb+ is less than at SYNCb–.
SYSREF+, SYSREF– 23, 24
ADC16DX370 pin_SYSREF.gif
Differential SYSREF signal input pins
Each pin is internally terminated to a DC bias with a 1-kΩ resistor. An external 100-Ω differential termination must always be provided. AC coupling using capacitors is required for coupling the SYSREF signal to these pins if the clock driver cannot meet the common-mode requirements. In the case of AC coupling, the termination must be placed on the source side of the coupling capacitors.
VA1.2 8, 21, 30, 50 Supply input pin 1.2-V analog power supply pins
These pins must be connected to a quiet source and decoupled to AGND with a 0.1-μF and 0.01-μF capacitor located close to each pin.
VA1.8 7, 15, 20, 29, 51, 56 Supply input pin 1.8-V analog power supply pins
These pins must be connected to a quiet source and decoupled to AGND with a 0.1-μF and 0.01-μF capacitor located close to each pin.
VA3.0 2, 13, 42 Supply input pin 3.0-V analog power supply pin
This pin must be connected to a quiet source and decoupled to AGND with a 0.1-μF and 0.01-μF capacitor located close to the pin.
VCMA, VCMB 1, 14
ADC16DX370 pin_VCM.gif
Input interface common mode voltage for channels A and B
These pins must be bypassed to AGND with low equivalent series inductance (ESL) 0.1-μF capacitors. One capacitor should be placed as close to the pin as possible and additional capacitors placed at the bias load points. 10-μF capacitors should also be placed in parallel. TI recommends to use VCMA and VCMB to provide the common mode voltage for the differential analog inputs. The input common mode bias is provided internally for the ADC input; therefore, external use of VCMA and VCMB is recommended, but not strictly required. The recommended bypass capacitors are always required.
VD1.2 26, 45 Supply input pin 1.2-V digital power supply pin
This pin must be connected to a quiet source and decoupled to AGND with a 0.1-μF and 0.01-μF capacitor located close to each pin.
VINA+, VINA– 4, 5
ADC16DX370 pin_VIN.gif
Differential analog input pins of channel A
Each input pin is terminated to the internal common mode reference with a resistor for an internal differential termination.
VINB+, VINB– 11, 10 Differential analog input pins of channel B
Each input pin is terminated to the internal common mode reference with a resistor for an internal differential termination.
0 Exposed thermal pad Exposed thermal pad
The exposed pad must be connected to the AGND ground plane electrically and with good thermal dissipation properties to achieve rated performance.