JAJSQJ6 December   2023 ADS1114L , ADS1115L

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  8. Parameter Measurement Information
    1. 7.1 Noise Performance
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Multiplexer
      2. 8.3.2 Analog Inputs
      3. 8.3.3 Full-Scale Range (FSR) and LSB Size
      4. 8.3.4 Voltage Reference
      5. 8.3.5 Oscillator
      6. 8.3.6 Output Data Rate and Conversion Time
      7. 8.3.7 Digital Comparator
      8. 8.3.8 Conversion-Ready Pin
      9. 8.3.9 SMBus Alert Response
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset and Power-Up
      2. 8.4.2 Operating Modes
        1. 8.4.2.1 Single-Shot Mode
        2. 8.4.2.2 Continuous-Conversion Mode
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
        1. 8.5.1.1 I2C Address Selection
        2. 8.5.1.2 I2C Interface Speed
          1. 8.5.1.2.1 Serial Clock (SCL) and Serial Data (SDA)
        3. 8.5.1.3 I2C Data Transfer Protocol
        4. 8.5.1.4 Timeout
        5. 8.5.1.5 I2C General-Call (Software Reset)
      2. 8.5.2 Reading and Writing Register Data
        1. 8.5.2.1 Reading Conversion Data or the Configuration Register
        2. 8.5.2.2 Writing the Configuration Register
      3. 8.5.3 Data Format
  10. Register Map
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Basic Connections
      2. 10.1.2 Unused Inputs and Outputs
      3. 10.1.3 Single-Ended Inputs
      4. 10.1.4 Input Protection
      5. 10.1.5 Analog Input Filtering
      6. 10.1.6 Connecting Multiple Devices
      7. 10.1.7 Duty Cycling For Low Power
      8. 10.1.8 I2C Communication Sequence Example
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Power-Supply Sequencing
      2. 10.3.2 Power-Supply Decoupling
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Noise Performance

Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between modulator frequency and output data rate is called oversampling ratio (OSR). By increasing the OSR, and thus reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the input-referred noise drops when reducing the output data rate because more samples of the internal modulator are averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is particularly useful when measuring low-level signals.

Table 7-1 and Table 7-2 summarize the ADS111xL noise performance. Data are representative of typical noise performance at TA = 25°C with the inputs shorted together externally. Table 7-1 shows the input-referred noise in units of μVRMS for the conditions shown. The µVPP values are shown in parenthesis. Table 7-2 shows the effective resolution calculated from μVRMS values using Equation 1. The noise-free resolution calculated from peak-to-peak noise values using Equation 2 are shown in parenthesis.

Equation 1. Effective Resolution = ln (FSR / VRMS-Noise) / ln(2)
Equation 2. Noise-Free Resolution = ln (FSR / VPP-Noise) / ln(2)
Table 7-1 Noise in μVRMS (μVPP) at VDD = 3.3 V
DATA RATE
(SPS)
FSR (Full-Scale Range)
±6.144 V ±4.096 V ±2.048 V ±1.024 V ±0.512 V ±0.256 V
8 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (7.81)
16 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (7.81)
32 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (7.81)
64 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (7.81)
128 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (12.35)
250 187.5 (252.09) 125 (148.28) 62.5 (84.03) 31.25 (39.54) 15.62 (16.06) 7.81 (18.53)
475 187.5 (266.92) 125 (227.38) 62.5 (79.08) 31.25 (56.84) 15.62 (32.13) 7.81 (25.95)
860 187.5 (430.06) 125 (266.93) 62.5 (118.63) 31.25 (64.26) 15.62 (40.78) 7.81 (35.83)
Table 7-2 Effective Resolution from RMS Noise (Noise-Free Resolution from Peak-to-Peak Noise) at
VDD = 3.3 V
DATA RATE
(SPS)
FSR (Full-Scale Range)
±6.144 V ±4.096 V ±2.048 V ±1.024 V ±0.512 V ±0.256 V
8 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)
16 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)
32 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)
64 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)
128 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.33)
250 16 (15.57) 16 (15.75) 16 (15.57) 16 (15.66) 16 (15.96) 16 (14.75)
475 16 (15.49) 16 (15.13) 16 (15.66) 16 (15.13) 16 (14.95) 16 (14.26)
860 16 (14.8) 16 (14.9) 16 (15.07) 16 (14.95) 16 (14.61) 16 (13.8)