SBAS683B August   2014  – May 2020 ADS1120-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Multiplexer
      2. 8.3.2  Low-Noise PGA
        1. 8.3.2.1 PGA Common-Mode Voltage Requirements
        2. 8.3.2.2 Bypassing the PGA
      3. 8.3.3  Modulator
      4. 8.3.4  Digital Filter
      5. 8.3.5  Output Data Rate
      6. 8.3.6  Voltage Reference
      7. 8.3.7  Clock Source
      8. 8.3.8  Excitation Current Sources
      9. 8.3.9  Low-Side Power Switch
      10. 8.3.10 Sensor Detection
      11. 8.3.11 System Monitor
      12. 8.3.12 Offset Calibration
      13. 8.3.13 Power Supplies
      14. 8.3.14 Temperature Sensor
        1. 8.3.14.1 Converting from Temperature to Digital Codes
          1. 8.3.14.1.1 For Positive Temperatures (for Example, 50°C):
          2. 8.3.14.1.2 For Negative Temperatures (for Example, –25°C):
        2. 8.3.14.2 Converting from Digital Codes to Temperature
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
      2. 8.4.2 Conversion Modes
        1. 8.4.2.1 Single-Shot Mode
        2. 8.4.2.2 Continuous-Conversion Mode
      3. 8.4.3 Operating Modes
        1. 8.4.3.1 Normal Mode
        2. 8.4.3.2 Duty-Cycle Mode
        3. 8.4.3.3 Turbo Mode
        4. 8.4.3.4 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Ready (DRDY)
        4. 8.5.1.4 Data Input (DIN)
        5. 8.5.1.5 Data Output and Data Ready (DOUT/DRDY)
        6. 8.5.1.6 SPI Timeout
      2. 8.5.2 Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1 RESET (0000 011x)
        2. 8.5.3.2 START/SYNC (0000 100x)
        3. 8.5.3.3 POWERDOWN (0000 001x)
        4. 8.5.3.4 RDATA (0001 xxxx)
        5. 8.5.3.5 RREG (0010 rrnn)
        6. 8.5.3.6 WREG (0100 rrnn)
      4. 8.5.4 Reading Data
      5. 8.5.5 Sending Commands
      6. 8.5.6 Interfacing with Multiple Devices
    6. 8.6 Register Map
      1. 8.6.1 Configuration Registers
        1. 8.6.1.1 Configuration Register 0 (Address = 00h) [reset = 00h]
          1. Table 12. Configuration Register 0 Field Descriptions
        2. 8.6.1.2 Configuration Register 1 (Address = 01h) [reset = 00h]
          1. Table 13. Configuration Register 1 Field Descriptions
        3. 8.6.1.3 Configuration Register 2 (Address = 02h) [reset = 00h]
          1. Table 15. Configuration Register 2 Field Descriptions
        4. 8.6.1.4 Configuration Register 3 (Address = 03h) [reset = 00h]
          1. Table 16. Configuration Register 3 Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Analog Input Filtering
      3. 9.1.3 External Reference and Ratiometric Measurements
      4. 9.1.4 Establishing a Proper Common-Mode Input Voltage
      5. 9.1.5 Unused Inputs and Outputs
      6. 9.1.6 Pseudo Code Example
    2. 9.2 Typical Applications
      1. 9.2.1 K-Type Thermocouple Measurement (–200°C to +1250°C)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 3-Wire RTD Measurement (–200°C to +850°C)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Design Variations for 2-Wire and 4-Wire RTD Measurements
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Bridge Measurement
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Sequencing
    2. 10.2 Power-Supply Ramp Rate
    3. 10.3 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Noise Performance

Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between modulator frequency and output data rate is called oversampling ratio (OSR). By increasing the OSR, and thus reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the input-referred noise drops when reducing the output data rate because more samples of the internal modulator are averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is particularly useful when measuring low-level signals.

Table 1 to Table 4 summarize the device noise performance. Data are representative of typical noise performance at TA = 25°C using the internal 2.048-V reference. Data shown are the result of averaging readings from a single device over a time period of approximately 0.75 seconds and are measured with the inputs internally shorted together. Table 1 and Table 3 list the input-referred noise in units of μVRMS for the conditions shown. Note that µVPP values are shown in parenthesis. Table 2 and Table 4 list the corresponding data in effective number of bits (ENOB) calculated from μVRMS values using Equation 1. Note that noise-free bits calculated from peak-to-peak noise values are shown in parenthesis.

The input-referred noise (Table 1 and Table 3) only changes marginally when using an external low-noise reference, such as the REF5020A-Q1. To calculate ENOB numbers and noise-free bits when using a reference voltage other than 2.048 V, use Equation 1 to Equation 3:

Equation 1. ENOB = ln (Full-Scale Range / VRMS-Noise) / ln(2)
Equation 2. Noise-Free Bits = ln (Full-Scale Range / VPP-Noise) / ln(2)
Equation 3. Full-Scale Range = 2 · VREF / Gain

Table 1. Noise in μVRMS (μVPP)
at AVDD = 3.3 V, AVSS = 0 V, and Internal Reference = 2.048 V

DATA RATE
(SPS)		 GAIN (PGA ENABLED)
1 2 4 8 16 32 64 128
20 62.50 (62.50) 31.25 (31.25) 15.63 (15.63) 7.81 (7.81) 3.91 (3.91) 1.95 (1.95) 0.98 (0.98) 0.49 (0.49)
45 62.50 (62.50) 31.25 (31.25) 15.63 (15.63) 7.81 (7.81) 3.91 (3.91) 1.95 (1.95) 0.98 (0.98) 0.49 (0.51)
90 62.50 (62.50) 31.25 (31.25) 15.63 (15.63) 7.81 (7.81) 3.91 (3.91) 1.95 (2.14) 0.98 (1.22) 0.49 (0.85)
175 62.50 (63.72) 31.25 (34.06) 15.63 (17.76) 7.81 (11.20) 3.91 (5.13) 1.95 (3.09) 0.98 (2.14) 0.49 (1.60)
330 62.50 (106.93) 31.25 (50.78) 15.63 (26.25) 7.81 (14.13) 3.91 (7.52) 1.95 (4.66) 0.98 (2.69) 0.49 (1.99)
600 62.50 (151.61) 31.25 (72.27) 15.63 (39.43) 7.81 (19.26) 3.91 (12.77) 1.95 (6.87) 0.98 (4.76) 0.55 (3.34)
1000 62.50 (227.29) 31.25 (122.68) 15.63 (58.53) 7.81 (31.52) 3.91 (18.08) 1.95 (10.71) 1.03 (6.52) 0.70 (4.01)
2000 62.50 (265.14) 31.25 (127.32) 15.63 (65.43) 7.81 (37.02) 3.91 (18.89) 1.95 (12.00) 1.13 (7.60) 0.82 (5.81)

Table 2. ENOB from RMS Noise (Noise-free Bits from Peak-to-Peak Noise)
at AVDD = 3.3 V, AVSS = 0 V, and Internal Reference = 2.048 V

DATA RATE
(SPS)		 GAIN (PGA ENABLED)
1 2 4 8 16 32 64 128
20 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)
45 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.49)
90 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.87) 16 (15.67) 16 (15.20)
175 16 (15.97) 16 (15.88) 16 (15.82) 16 (15.48) 16 (15.61) 16 (15.34) 16 (14.87) 16 (14.29)
330 16 (15.23) 16 (15.30) 16 (15.25) 16 (15.15) 16 (15.05) 16 (14.74) 16 (14.54) 16 (13.97)
600 16 (14.72) 16 (14.79) 16 (14.66) 16 (14.70) 16 (14.29) 16 (14.18) 16 (13.72) 15.83 (13.23)
1000 16 (14.14) 16 (14.03) 16 (14.09) 16 (13.99) 16 (13.79) 16 (13.54) 15.92 (13.26) 15.49 (12.96)
2000 16 (13.92) 16 (13.97) 16 (13.93) 16 (13.76) 16 (13.73) 16 (13.38) 15.79 (13.04) 15.25 (12.43)

Table 3. Noise in μVRMS (μVPP) with PGA Disabled
at AVDD = 3.3 V, AVSS = 0 V, and Internal Reference = 2.048 V

DATA RATE
(SPS)		 GAIN (PGA DISABLED)
1 2 4
20 62.50 (62.50) 31.25 (31.25) 15.63 (15.63)
45 62.50 (62.50) 31.25 (31.25) 15.63 (15.63)
90 62.50 (62.50) 31.25 (31.25) 15.63 (15.63)
175 62.50 (65.92) 31.25 (35.40) 15.63 (18.92)
330 62.50 (94.24) 31.25 (50.17) 15.63 (28.75)
600 62.50 (138.67) 31.25 (78.13) 15.63 (39.79)
1000 62.50 (260.50) 31.25 (120.97) 15.63 (63.72)
2000 62.50 (250.98) 31.25 (131.35) 15.63 (68.18)

Table 4. ENOB from RMS Noise (Noise-free Bits from Peak-to-Peak Noise) with PGA Disabled
at AVDD = 3.3 V, AVSS = 0 V, and Internal Reference = 2.048 V

DATA RATE
(SPS)		 GAIN (PGA DISABLED)
1 2 4
20 16 (16) 16 (16) 16 (16)
45 16 (16) 16 (16) 16 (16)
90 16 (16) 16 (16) 16 (16)
175 16 (15.92) 16 (15.82) 16 (15.72)
330 16 (15.41) 16 (15.32) 16 (15.12)
600 16 (14.85) 16 (14.68) 16 (14.65)
1000 16 (13.94) 16 (14.05) 16 (13.97)
2000 16 (13.99) 16 (13.93) 16 (13.87)