JAJSO07B December   2012  – April 2022 ADS54T01

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics
    7. 7.7  Electrical Characteristics
    8. 7.8  Electrical Characteristics
    9. 7.9  Electrical Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Test Pattern Output
      2. 8.3.2  Clock Inputs
      3. 8.3.3  SNR and Clock Jitter
      4. 8.3.4  Analog Inputs
      5. 8.3.5  Over-Range Indication
      6. 8.3.6  Interleaving Correction
      7. 8.3.7  High-Resolution Output Data
      8. 8.3.8  Low-Resolution Output Data
      9. 8.3.9  Full Speed – 7 Bit
      10. 8.3.10 Decimated Low-Resolution Output Data
      11. 8.3.11 Multi Device Synchronization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
      2. 8.4.2 Feedback Mode: Burst Mode
      3. 8.4.3 Receive Mode: Decimation Filter
      4. 8.4.4 Manual Trigger Mode
      5. 8.4.5 Auto Trigger Mode
    5. 8.5 Programming
      1. 8.5.1 Device Initialization
      2. 8.5.2 Serial Register Write
      3. 8.5.3 Serial Register Readout
    6. 8.6 Register Maps
      1. 8.6.1 Serial Register Map
      2. 8.6.2 Description of Serial Interface Registers
  9. 9 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.1 Test Pattern Output

The ADS54T01 can be configured to output different test patterns that can be used to verify the digital interface is connected and working properly.

To enable the test pattern mode, the high-performance mode 1 has to be disabled first through the SPI register write. Then different test patterns can be selected by configuring registers x3C, x3D, and x3E. All three registers must be configured for the test pattern to work properly.

First set HP1 = 0 (Addr 0x01, D01)

Internally the test pattern replaces the sampled data from the ADC. However at the LVDS outputs the output data is still subject to burst mode operation. In low-resolution output, the LSBs of the test pattern are replaced with 0 s.

GUID-1A02DC4E-503F-49C1-8B15-F90E408B50E1-low.gifFigure 8-2 Test Pattern Selection
Table 8-1 Test Pattern Register Setting
Register AddressAll 0sAll 1sToggle (0xAAA => 0x555)Toggle (0xFFF => 0x000)
0x3C0x80000xBFFC0x95540xBFFC
0x3D0x00000x3FFC0x2AA80x0000
0x3E0x00000x3FFC0x15540x3FFC
Table 8-2 Custom Pattern Register Setting
Register AddressCustom Pattern
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
x3C10D11D10D9D8D7D6D5D4D3D2D1D000
x3D0000
x3E0000

For normal operation, set HP1 = 1 (Addr 0x01, D01) and 0x3C, 0x3D, and 0x3E all to 0.