SBAS682D November   2014  – December 2015 ADS7044

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Digital Voltage Levels
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference
      2. 8.3.2 Analog Input
      3. 8.3.3 ADC Transfer Function
      4. 8.3.4 Serial Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration
        1. 8.4.1.1 Offset Calibration on Power-Up
        2. 8.4.1.2 Offset Calibration During Normal Operation
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Single-Supply DAQ with the ADS7044
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Antialiasing Filter
          2. 9.2.1.2.2 Input Amplifier Selection
          3. 9.2.1.2.3 Reference Circuit
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Ultra-Low Power and Ultra-Small, High CMRR DAQ Circuit with the ADS7044
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power-Supply Recommendations
    1. 10.1 AVDD and DVDD Supply Recommendations
    2. 10.2 Estimating Digital Power Consumption
    3. 10.3 Optimizing Power Consumed by the Device
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
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  • RUG|8
サーマルパッド・メカニカル・データ
発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The two primary circuits required to maximize the performance of a high-precision, successive approximation register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This section details some general principles for designing the input driver circuit, reference driver circuit, and provides some application circuits designed for the ADS7044.

9.2 Typical Applications

9.2.1 Single-Supply DAQ with the ADS7044

ADS7044 apps_1_sbas682.gif Figure 39. DAQ Circuit: Single-Supply DAQ

9.2.1.1 Design Requirements

The goal of this application is to design a single-supply digital acquisition (DAQ) circuit based on the ADS7044 with SNR greater than 71 dB and THD less than –85 dB for a differential input signal having an amplitude of AVDD with a common-mode voltage of AVDD / 2 and input frequencies of 5 kHz at a throughput of
1 MSPS.

9.2.1.2 Detailed Design Procedure

The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and an antialiasing filter. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a high-precision ADC.

9.2.1.2.1 Antialiasing Filter

Converting analog-to-digital signals requires sampling an input signal at a rate greater than or equal to the Nyquist rate. Any higher frequency content in the input signal beyond half the sampling frequency is digitized and folded back into the low-frequency spectrum. This process is called aliasing. Therefore, an external, antialiasing filter must be used to remove the harmonic content from the input signal before being sampled by the ADC. An antialiasing filter is designed as a low-pass RC filter, for which the 3-dB bandwidth is optimized for noise, response time, and throughput. For dc signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow the signal to be accurately set at the ADC inputs during the small acquisition time window. Figure 40 provides the equation for determining the bandwidth of antialiasing filter.

ADS7044 apps_aaf_de_sbas682.gif Figure 40. Antialiasing Filter

For ac signals, the filter bandwidth must be kept low to band limit the noise fed into the ADC input, thereby increasing the signal-to-noise ratio (SNR) of the system. Besides filtering the noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC. A filter capacitor, CFLT, is connected across the ADC inputs. This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor must be at least 20 times the specified value of the ADC sampling capacitance. For this device, the input sampling capacitance is equal to 15 pF. Thus, the value of CFLT must be greater than 300 pF. The capacitor must be a COG- or NPO-type because these capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time.

Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability and distortion of the design.

The input amplifier bandwidth must be much higher than the cutoff frequency of the antialiasing filter. TI strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers may require more bandwidth than others to drive similar filters.

9.2.1.2.2 Input Amplifier Selection

Selection criteria for the input amplifiers is highly dependent on the input signal type and the performance goals of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate amplifier to drive the inputs of the ADC are:

  • Small-signal bandwidth: Select the small-signal bandwidth of the input amplifiers to be high enough to settle the input signal in the acquisition time of the ADC. Higher bandwidth reduces the closed-loop output impedance of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter at the ADC inputs. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. In order to maintain the overall stability of the input driver circuit, select the amplifier bandwidth as described in Equation 2:
  • Equation 2. ADS7044 q_gbw_sbas682.gif

    where

    • GBW = Unity-gain bandwidth
  • Noise: Noise contribution of the front-end amplifiers must be low enough to prevent any degradation in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data acquisition system is not limited by the front-end circuit, keep the total noise contribution from the front-end circuit below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is band limited by designing a low cutoff frequency RC filter, as explained in Equation 3.
  • Equation 3. ADS7044 q_noise_sbas682.gif

    where

    • V1/f_AMP_PP is the peak-to-peak flicker noise in µVrms,
    • en_RMS is the amplifier broadband noise,
    • f–3dB is the –3-dB bandwidth of the RC filter,
    • k is the Boltzmann's constant, and
    • T is absolute temperature in kelvin.
    • For symmetrical feedback, β = R1 / (R1 + R2) = R3 / (R3 + R4).
    • For details on noise analysis, refer to the technical brief Analysis of fully differential amplifiers (SLYT157)
  • Settling time: For dc signals with fast transients that are common in a multiplexed application, the input signal must settle to the desired accuracy at the inputs of the ADC during the acquisition time window. This condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the desired accuracy. Therefore, always verify the settling behavior of the input driver with TINA™-SPICE simulations before selecting the amplifier.

The OPA316 is selected for this application for its rail-to-rail input and output swing, low-noise (11 nV/√Hz), and low-power (400 µA) performance to support a single-supply data acquisition circuit.

9.2.1.2.3 Reference Circuit

The analog supply voltage of the device is also used as a voltage reference for conversion. TI recommends decoupling the AVDD pin with a 1-µF, low-ESR ceramic capacitor. The minimum capacitor value required for AVDD is 200 nF.

ADS7044 apps_tipd_logo_bas557.gif

For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision Design TIPD168, Three 12-Bit Data Acquisition Reference Designs Optimized for Low Power and Ultra-Small Form Factor (TIDU390).

9.2.1.3 Application Curve

Figure 41 shows the FFT plot for the device with a 5-kHz input frequency for the circuit in Figure 39.

ADS7044 C031_SBAS682.png
SNR = 72.2 dB THD = –85.7 dB SINAD = 72 dB
Number of samples = 8192
Figure 41. Test Results for the ADS7044 and OPA316 for a 5-kHz Input

9.2.2 Ultra-Low Power and Ultra-Small, High CMRR DAQ Circuit with the ADS7044

ADS7044 apps_2_sbas682.gif Figure 42. ADS7044 DAQ Circuit

9.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 4 as input parameters.

Table 4. Design Parameters

DESIGN PARAMETER GOAL VALUE
SINAD 71 dB
Throughput 1 MSPS
AVDD 3.3 V
AVDD current consumption 800 µA (at a 5-kHz fIN) and 1500 µA (at a 25-kHz fIN)
VIN to the THS4531A –AVDD to AVDD
Common-mode voltage for VIN to the THS4531A 0 V to AVDD / 2

9.2.2.2 Detailed Design Procedure

See the Detailed Design Procedure section in the Single-Supply DAQ with the ADS7044 application for further details.

To achieve a SINAD of 71 dB, the operational amplifier must have high bandwidth to settle the input signal within the acquisition time of the ADC. The operational amplifier must have low noise to keep the total system noise below 20% of the input-referred noise of the ADC.

For the application circuit shown in Figure 42, the THS4531A is selected for its high bandwidth (36 MHz), low noise (10 nV/√Hz), and for its capability to set the common-mode voltage for the ADC. The THS4531A rejects the variation of common-mode at its input and provides a CMRR of 90 dB (min).

9.2.2.3 Application Curves

Figure 43 shows the FFT plot for the device with a 5-kHz input frequency for the circuit in Figure 42. Figure 44 shows the FFT plot for the device with a 25-kHz input frequency for the circuit in Figure 42.

ADS7044 C032_SBAS682.png
SNR = 72.3 dB THD = –87.8 dB SINAD = 72.2 dB
AVDD current = 740 µA, Number of samples = 8192
Figure 43. Test Results for the ADS7044 and THS4531A for a 5-kHz Input
ADS7044 C033_SBAS682.png
SNR = 71.6 dB THD = –85 dB SINAD = 71.4 dB
AVDD current = 1375 µA, Number of samples = 8192
Figure 44. Test Results for the ADS7044 and THS4531A for a 25-kHz Input