JAJSFT4C August   2018  – June 2019 ADS9224R , ADS9234R

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: ADS92x4R
    6. 6.6  Electrical Characteristics: ADS9224R
    7. 6.7  Electrical Characteristics: ADS9234R
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics: ADS9224R
    11. 6.11 Typical Characteristics: ADS9234R
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Converter Modules
        1. 7.3.1.1 Analog Input With Sample-and-Hold
        2. 7.3.1.2 ADC Transfer Function
      2. 7.3.2 Internal Reference Voltage
      3. 7.3.3 Reference Buffers
      4. 7.3.4 REFby2 Buffer
      5. 7.3.5 Data Averaging
        1. 7.3.5.1 Averaging of Two Samples
        2. 7.3.5.2 Averaging of Four Samples
    4. 7.4 Device Functional Modes
      1. 7.4.1 ACQ State
      2. 7.4.2 CNV State
      3. 7.4.3 Reset or Power-Down
        1. 7.4.3.1 Reset
        2. 7.4.3.2 Power-Down
      4. 7.4.4 Conversion Control and Data Transfer Frame
        1. 7.4.4.1 Conversion Control and Data Transfer Frame With Zero Cycle Latency (Zone 1 Transfer)
        2. 7.4.4.2 Conversion Control and Data Transfer Frame With Wide Read Cycle (Zone 2 Transfer)
    5. 7.5 READY/STROBE Output
      1. 7.5.1 READY Output
      2. 7.5.2 STROBE Output
    6. 7.6 Programming
      1. 7.6.1 Output Data Word
      2. 7.6.2 Data Transfer Protocols
        1. 7.6.2.1 Protocols for Reading From the Device
          1. 7.6.2.1.1 Legacy, SPI-Compatible Protocols (SPI-xy-S-SDR)
          2. 7.6.2.1.2 SPI-Compatible Protocols With Bus Width Options and Single Data Rate (SPI-xy-D-SDR and SPI-xy-Q-SDR)
          3. 7.6.2.1.3 SPI-Compatible Protocols With Bus Width Options and Double Data Rate (SPI-x1-S-DDR, SPI-x1-D-DDR, SPI-x1-Q-DDR)
          4. 7.6.2.1.4 Clock Re-Timer (CRT) Protocols (CRT-S-SDR, CRT-D-SDR, CRT-Q-SDR, CRT-S-DDR, CRT-D-DDR, CRT-Q-DDR)
          5. 7.6.2.1.5 Parallel Byte Protocols (PB-xy-AB-SDR, PB-xy-AA-SDR)
        2. 7.6.2.2 Device Setup
          1. 7.6.2.2.1 Single Device: All Enhanced-SPI Options
          2. 7.6.2.2.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 7.6.2.3 Protocols for Configuring the Device
      3. 7.6.3 Reading and Writing Registers
    7. 7.7 Register Maps
      1. 7.7.1 ADS92x4R Registers
        1. 7.7.1.1 DEVICE_STATUS Register (Offset = 0h) [reset = 0h]
          1. Table 12. DEVICE_STATUS Register Field Descriptions
        2. 7.7.1.2 POWER_DOWN_CFG Register (Offset = 1h) [reset = 0h]
          1. Table 13. POWER_DOWN_CFG Register Field Descriptions
        3. 7.7.1.3 PROTOCOL_CFG Register (Offset = 2h) [reset = 0h]
          1. Table 14. PROTOCOL_CFG Register Field Descriptions
        4. 7.7.1.4 BUS_WIDTH Register (Offset = 3h) [reset = 0h]
          1. Table 15. BUS_WIDTH Register Field Descriptions
        5. 7.7.1.5 CRT_CFG Register (Offset = 4h) [reset = 0h]
          1. Table 16. CRT_CFG Register Field Descriptions
        6. 7.7.1.6 OUTPUT_DATA_WORD_CFG Register (Offset = 5h) [reset = 0h]
          1. Table 17. OUTPUT_DATA_WORD_CFG Register Field Descriptions
        7. 7.7.1.7 DATA_AVG_CFG Register (Offset = 6h) [reset = 0h]
          1. Table 18. DATA_AVG_CFG Register Field Descriptions
        8. 7.7.1.8 REFBY2_OFFSET Register (Offset = 7h) [reset = 0h]
          1. Table 19. REFBY2_OFFSET Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Input Driver
        1. 8.1.1.1 Charge-Kickback Filter
      2. 8.1.2 Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 関連資料
    3. 11.3 関連リンク
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 コミュニティ・リソース
    6. 11.6 商標
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Switching Characteristics

at AVDD = 4.5 V to 5.5V, DVDD = 2.35 V to 5.5 V, VCM = VREF/2, Internal reference and maximum throughput (unless otherwise noted); minimum and maximum values at TA = -40℃ to +125℃; typical values at TA = 25℃, AVDD = 5V, DVDD = 3.3 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CONVERSION CONTROL AND DATA TRANSFER (See Figure 1  and  Figure 2)
tDRDY Data ready time for present sample: CONVST high to READY high Zero cycle latency (zone 1 transfer) for ADS9224R 315 ns
Data ready time for present sample: CONVST high to READY high Zero cycle latency (zone 1 transfer) for ADS9234R 280 ns
SPI-COMPATIBLE AND PARALLEL BYTE PROTOCOL (See Figure 3)
tDEN_CSDO Delay time: CS falling to data valid on SDO-x 12 ns
tDZ_CSDO Delay time: CS rising edge to SDO-x tristate 12 ns
tD_CKDO Delay time: SCLK launch edge to next data valid on SDO-x SPI-compatible protocols with single data rate 15.8 ns
tD_CKDO Delay time: SCLK launch edge to next data valid on SDO-x SPI-compatible protocols with double data rate 21 ns
tD_CKDO Delay time: SCLK launch edge to next data valid on SDO-x  Parallel byte protocol 21 ns
tA Aperture delay 8 ns
tA mismatch 40 ps
tJITTER Aperture jitter 2 ps
CLOCK RE-TIMER PROTOCOL WITH STROBE = SCLK (EXTERNAL CLOCK)(1)(See Figure 4)
tOFF_STROBE_DO Time offset: STROBE edge to next data valid on SDO-x -2.5 2.5 ns
tD_CS_READY Delay time: CS rising to READY displaying internal device state 13.5 ns
tD_CKSTROBE_r Delay time: SCLK rising edge to STROBE rising 21.5 ns
tD_CKSTROBE_f Delay time: SCLK falling edge to STROBE falling 21.5 ns
tPH_STROBE Strobe output high time 0.45 × tSTR 0.55 × tSTR ns
tPL_STROBE Strobe output low time 0.45  × tSTR 0.55 × tSTR ns
CLOCK RE-TIMER PROTOCOL WITH STROBE = INTERNAL CLOCK (1)(See Figure 5)
tD_CS_STROBE Delay time : CS falling to 1st STROBE rising 15 50 ns
tOFF_STROBE_DO Time offset : STROBE edge to next data valid on SDO-x -2.5 2.5 ns
tD_CS_READY Delay time: CS rising to READY displaying internal device state 13.5 ns
tINTCLK INTCLK period 15 ns
tSTR STROBE period INTCLK 16 ns
INTCLK / 2 30 ns
INTCLK / 4 60 ns
tWH_STR STROBE high period 0.45 × tSTR 0.55 × tSTR ns
tWL_STR STROBE low period 0.45 × tSTR 0.55 × tSTR ns
ASYNCHRONOUS RESET AND POWER-DOWN TIMING (See Figure 6)
tRST-WKUP Wake up time from reset 1 µs
tPD-WKUP(1) Wake up time from power-down 18 150 ms
tWKUP-REFOUT REFOUT wake-up time 15.6 140 ms
tREFP_x-SETTLE Reference buffer output settling time CREFP_x = 10µF 18 150 ms
With CREFP_x = 10µF
ADS9224R ADS9234R timing-conv-zone1-sbas876.gif
The READY output is required for data transfer with zero cycle latency. The STROBE output is required only for clock re-timer (CRT) protocols.
Figure 1. Conversion Control and Data Transfer With Zero Cycle Latency (Zone 1 Transfer)
ADS9224R ADS9234R timing-conv-zone2-sbas876.gif
The READY output is not required for zone 2 data transfer. The STROBE output is required only for clock re-timer protocols.
Figure 2. Conversion Control and Data Transfer With Wider Read Cycle (Zone 2 Transfer)
ADS9224R ADS9234R timing-spi-sbas876.gif
The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected. DDR is not supported with the parallel byte protocol.
Figure 3. SPI-Compatible and Parallel Byte Protocols Timing
ADS9224R ADS9234R timing-crt-ext-SBAS876.gifFigure 4. Clock Re-Timer Protocol (External Clock) Timing
ADS9224R ADS9234R timing-crt-int-SBAS876.gifFigure 5. Clock Re-Timer Protocol (Internal Clock) Timing
ADS9224R ADS9234R timing_rst_pd_sbas842.gifFigure 6. Asynchronous Reset and Power-Down Timing