JAJSLP3 june   2023 AFE43902-Q1 , AFE53902-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: ADC Input
    7. 6.7  Electrical Characteristics: General
    8. 6.8  Timing Requirements: I2C Standard Mode
    9. 6.9  Timing Requirements: I2C Fast Mode
    10. 6.10 Timing Requirements: I2C Fast Mode Plus
    11. 6.11 Timing Requirements: SPI Write Operation
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    14. 6.14 Timing Requirements: PWM Output
    15. 6.15 Timing Diagrams
    16. 6.16 Typical Characteristics: Voltage Output
    17. 6.17 Typical Characteristics: ADC
    18. 6.18 Typical Characteristics: General
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Analog Front End (AFE) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.3.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.3.1.2 NVM-CRC-FAIL-INT Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 External Reset
      6. 7.3.6 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital-to-Analog Converter (DAC) Mode
        1. 7.4.1.1 Voltage Reference and DAC Transfer Function
          1. 7.4.1.1.1 Power-Supply as Reference
          2. 7.4.1.1.2 Internal Reference
          3. 7.4.1.1.3 External Reference
      2. 7.4.2 Pulse-Width Modulation (PWM) Mode
      3. 7.4.3 Analog-to-Digital Converter (ADC) Mode
      4. 7.4.4 Multislope Thermal Foldback Mode
        1. 7.4.4.1 Thermistor Linearization
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0400h]
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh) [reset = 03F9h]
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0001h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 2068h]
      7. 7.6.7  DEVICE-MODE-CONFIG Register (address = 25h) [reset = 8040h]
      8. 7.6.8  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      9. 7.6.9  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      10. 7.6.10 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      11. 7.6.11 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      12. 7.6.12 Xx-TEMPERATURE Register (SRAM address = 20h, 22h, 24h) [reset = 0000h]
      13. 7.6.13 Yx-TEMPERATURE Register (SRAM address = 21h, 23h, 25h) [reset = 0000h]
      14. 7.6.14 Xx-OUTPUT Register (SRAM address = 26h, 28h, 2Ah, 2Ch) [reset = 0000h]
      15. 7.6.15 Yx-OUTPUT Register (SRAM address = 27h, 29h, 2Bh, 2Dh) [reset = 0000h]
      16. 7.6.16 PWM-FREQUENCY Register (SRAM address = 2Eh) [reset = 0000h]
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Multislope Thermal Foldback Using the AFE53902-Q1 and Voltage Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Multislope Thermal Foldback Using the AFE43902-Q1 and PWM Output
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Performance Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Typical Characteristics: Voltage Output

at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1 ×, and DAC outputs unloaded (unless otherwise noted)

GUID-20230126-SS0I-QLNN-DBKC-JJHPPRPC6XH9-low.svg
Internal reference, gain = 4 ×
Figure 6-4 Voltage Output INL vs Digital Input Code
GUID-20230126-SS0I-4WZQ-0CKG-N03Q5VWRGZNS-low.svg
 
Figure 6-6 Voltage Output INL vs Temperature
GUID-20230126-SS0I-1DQ8-4XFN-RLWRFCTH7F7Z-low.svg
Internal reference, gain = 4 ×
Figure 6-8 Voltage Output DNL vs Digital Input Code
GUID-20230126-SS0I-KLMC-BPSL-WLK8LL0VD6NK-low.svg
 
Figure 6-10 Voltage Output DNL vs Temperature
GUID-20230126-SS0I-L3HQ-DS2S-S0F43BKXPK1L-low.svg
Internal reference, gain = 4 ×
Figure 6-12 Voltage Output TUE vs Digital Input Code
GUID-20220410-SS0I-HL85-XWZD-X3DHT7824VLT-low.svg
DAC channels at midscale
Figure 6-14 Voltage Output TUE vs Temperature
GUID-20220410-SS0I-VRN3-DSBQ-4ZJ4TSPRDTWS-low.svg
 
Figure 6-16 Voltage Output Offset Error vs Temperature
GUID-20220410-SS0I-RCS9-Z0SB-C7XS371JFDCB-low.svg
DAC channels at midscale
Figure 6-18 Voltage Output vs Load Current
GUID-20230126-SS0I-7WW1-HBF2-TSNBKVFW1MVP-low.svg
 
Figure 6-20 Voltage Output Code-to-Code Glitch - Rising Edge
GUID-20220410-SS0I-P6RZ-WCS0-TH4H7GDGR4GT-low.svg
Zero scale to full scale swing 
Figure 6-22 Voltage Output Setting Time - Rising Edge
GUID-20220410-SS0I-HWHM-QTB2-HCZF9CZPB39X-low.svg
DAC in Hi-Z power-down mode
Figure 6-24 Voltage Output Power-On Glitch
GUID-20220410-SS0I-CG68-XTL7-MDGLNLDQMQKZ-low.svg
Internal reference, gain = 4 ×
Figure 6-26 Voltage Output Noise Density
GUID-20220410-SS0I-9PTT-1N7B-NSSN0MRDPJ8Z-low.svg
Internal reference, gain = 4x, f = 0.1 Hz to 10 Hz
Figure 6-28 Voltage Output Flicker Noise
GUID-20230126-SS0I-VL8Z-PXHX-6C8VNK8GLH3C-low.svg
 
Figure 6-5 Voltage Output INL vs Digital Input Code
GUID-20230126-SS0I-43CR-PGPC-JFFBC8KTWTLD-low.svg
 
Figure 6-7 Voltage Output INL vs Supply Voltage
GUID-20230126-SS0I-4WHS-Z09L-DHQGDQLBT7DP-low.svg
 
Figure 6-9 Voltage Output DNL vs Digital Input Code
GUID-20230126-SS0I-PTHL-DSDM-GLNBH5PGH1WN-low.svg
 
Figure 6-11 Voltage Output DNL vs Supply Voltage
GUID-20230126-SS0I-9F3K-LB85-S4KPMXGC2RRS-low.svg
 
Figure 6-13 Voltage Output TUE vs Digital Input Code
GUID-20220410-SS0I-7P3Z-XZ4M-JW1KSGKKCPRW-low.svg
DAC channels at midscale
Figure 6-15 Voltage Output TUE vs Supply Voltage
GUID-20220410-SS0I-SW9H-W36R-4CJVPBNR12GD-low.svg
 
Figure 6-17 Voltage Output Gain Error vs Temperature
GUID-20220410-SS0I-JVXQ-PZT4-WB6F2NVHQWR8-low.svg
 
Figure 6-19 Voltage Output AC PSRR vs Frequency
GUID-20230126-SS0I-2RJQ-3H80-DJSWZWK8GTQF-low.svg
 
Figure 6-21 Voltage Output Code-to-Code Glitch - Falling Edge
GUID-20220410-SS0I-9TH4-GTX4-BT0DZTK5H5G5-low.svg
Full scale to zero scale swing
Figure 6-23 Voltage Output Setting Time - Falling Edge
GUID-20220410-SS0I-XFFT-CQ3W-H4BNPNG6G8WC-low.svg
DAC at zero scale 
Figure 6-25 Voltage Output Power-Off Glitch
GUID-20220410-SS0I-GVRF-VW2W-0KSMJHT8DP0G-low.svg
 
Figure 6-27 Voltage Output Noise Density
GUID-20220410-SS0I-XQMG-WLWC-ZJ78JSHHHHV3-low.svg
f = 0.1 Hz to 10 Hz 
Figure 6-29 Voltage Output Flicker Noise