JAJSP45 September   2023 AMC130M02

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Insulation Specifications
    6. 6.6  Safety-Related Certifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  8. Parameter Measurement Information
    1. 7.1 Noise Measurements
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Isolated DC/DC Converter
        1. 8.3.1.1 DC/DC Converter Failure Detection
      2. 8.3.2  High-Side Current Drive Capability
      3. 8.3.3  Isolation Channel Signal Transmission
      4. 8.3.4  Input ESD Protection Circuitry
      5. 8.3.5  Input Multiplexer
      6. 8.3.6  Programmable Gain Amplifier (PGA)
      7. 8.3.7  Voltage Reference
      8. 8.3.8  Internal Test Signals
      9. 8.3.9  Clocking and Power Modes
      10. 8.3.10 ΔΣ Modulator
      11. 8.3.11 Digital Filter
        1. 8.3.11.1 Digital Filter Implementation
          1. 8.3.11.1.1 Fast-Settling Filter
          2. 8.3.11.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.11.2 Digital Filter Characteristic
      12. 8.3.12 Channel Phase Calibration
      13. 8.3.13 Calibration Registers
      14. 8.3.14 Register Map CRC
      15. 8.3.15 General-Purpose Digital Output (GPO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Start-Up Behavior After Power-Up
      3. 8.4.3 Start-Up Behavior After a Pin Reset or RESET Command
      4. 8.4.4 Start-Up Behavior After a Pause in CLKIN
      5. 8.4.5 Synchronization
      6. 8.4.6 Conversion Modes
        1. 8.4.6.1 Continuous-Conversion Mode
        2. 8.4.6.2 Global-Chop Mode
      7. 8.4.7 Power Modes
      8. 8.4.8 Standby Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  Short SPI Frames
        10. 8.5.1.10 Communication Cyclic Redundancy Check (CRC)
        11. 8.5.1.11 SPI Timeout
      2. 8.5.2 ADC Conversion Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1 NULL (0000 0000 0000 0000)
        2. 8.5.3.2 RESET (0000 0000 0001 0001)
        3. 8.5.3.3 STANDBY (0000 0000 0010 0010)
        4. 8.5.3.4 WAKEUP (0000 0000 0011 0011)
        5. 8.5.3.5 LOCK (0000 0101 0101 0101)
        6. 8.5.3.6 UNLOCK (0000 0110 0101 0101)
        7. 8.5.3.7 RREG (101a aaaa annn nnnn)
          1. 8.5.3.7.1 Reading a Single Register
          2. 8.5.3.7.2 Reading Multiple Registers
        8. 8.5.3.8 WREG (011a aaaa annn nnnn)
      4. 8.5.4 ADC Output Buffer and FIFO Buffer
      5. 8.5.5 Collecting Data for the First Time or After a Pause in Data Collection
    6. 8.6 AMC130M02 Registers
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Multiple Device Configuration
      5. 9.1.5 Calibration
      6. 9.1.6 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Voltage Measurement
        2. 9.2.2.2 Current Shunt Measurement
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Start-Up Behavior After Power-Up

The AMC130M02 does not generate conversion data automatically after power-up because the integrated DC/DC converter is disabled initially. For the ADC to operate, the DC/DC converter must be enabled after power-up, and a stable supply voltage at the HLDO_OUT pin must be established that serves as the power supply for the circuitry on the secondary (high) side.

A recommended procedure for powering up the AMC130M02 is described in this section. Figure 8-19 depicts a timing diagram for the device behavior when this recommended sequence is used. Figure 8-17 provides a flow diagram that displays the recommended sequence in a graphical form.

Follow these steps to ensure a correct start-up behavior at power-up:

  • Power up the DVDD supply.
  • The transition of DRDY from low to high indicates a valid supply voltage on the primary side is established, and also indicates the SPI interface is ready for communication.
  • Configure the clock divider by setting the CLK_DIV[1:0] bits in the CLOCK register as needed.
  • Configure the modulator clock frequency by setting the DCDC_FREQ[3:0] bits in the DCDC_CTRL register; see the Clocking and Power ModesClocking and Power ModesClocking and Power ModesClocking and Power Modes section for details.
  • Enable the DC/DC converter by setting the DCDC_EN bit in the DCDC_CTRL register to 1b.
  • Configure all other registers of the AMC130M02 before the external clock is applied to the CLKIN pin.
  • Provide the main clock at the CLKIN input to start operation of the integrated DC/DC converter, and to make sure that the secondary power supply at the HLDO_OUT pin is generated.
  • The transition of the SEC_FAIL bit in the STATUS register from high to low indicates that the secondary power supply at the HLDO_OUT pin is established and the ADC conversion data output is valid. Confirm device operation by reading the SEC_FAIL bit, and verify that this bit is set to 0b, before reading any conversion data from the ADC. There are two options for reading the SEC_FAIL bit in the STATUS register: sending a NULL command results in a response including the STATUS word, or sending a register read command to read the STATUS register. The SEC_FAIL bit is a latched bit; therefore, at least two read commands are required to confirm that this bit transitioned from high to low; the first read command clears the logic high value that is latched during device power-up. Use the second read command to verify that the SEC_FAIL bit is set to 0b, indicating that the secondary supply is valid. If the SEC_FAIL bit still reads 1b as a result of the second read command, continue reading the SEC_FAIL bit until this bit reads 0b before reading any conversion data from the ADC.

Regarding the conversion data after power-up, pay attention to the following:

  • The high-to-low transition of DRDY indicates that new conversion data are available. As given in Figure 8-19, ADC data are only valid if the SEC_FAIL reads 0b during the conversion period. The first two conversion results shown in Figure 8-19, represent invalid data.
  • When the ADC generates valid data, the digital filter must settle, as described in the SINC3 and SINC3 + SINC1 Filter section. Two subsequent conversion results illustrated in Figure 8-19 are unsettled (assuming OSR equals 1024), and the last conversion result shown provides valid and settled data.
  • For best control of the conversion timing, especially in a system where multiple devices of the AMC130M02 are used, trigger a synchronization using the SYNC/RESET pin before the host collects conversion data from the ADC. See the SynchronizationSynchronizationSynchronizationSynchronizationSynchronization section for more details regarding how to synchronize the device.

In Figure 8-19, tPOR_SEC is the time from enabling the DC/DC converter to the first falling edge of the SEC_FAIL bit, which indicates that the secondary power supply at the HLDO_OUT pin is stable. tPOR_DVDD is the time from DVDD supply at 90% to DRDY first rising edge.

GUID-20220118-SS0I-64KR-FH4H-QX9SJRSBDF2X-low.svg Figure 8-16 Start-Up Behavior at Power-Up and Settling Times, OSR = 1024
GUID-20230303-SS0I-TW61-QFMZ-BKJ0ZLBH69BN-low.svg Figure 8-17 Flow Diagram for Start-Up Procedure at Power-Up