JAJSHC4A May   2019  – November 2019 ATL431LI-Q1 , ATL432LI-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Temperature Coefficient
    2. 8.2 Dynamic Impedance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Open Loop (Comparator)
      2. 9.4.2 Closed Loop
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Comparator With Integrated Reference
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design Procedure
        1. 10.2.3.1 Basic Operation
          1. 10.2.3.1.1 Overdrive
        2. 10.2.3.2 Output Voltage and Logic Input Level
          1. 10.2.3.2.1 Input Resistance
      4. 10.2.4 Application Curves
      5. 10.2.5 Precision LED Lighting Current Sink Regulator
        1. 10.2.5.1 Design Requirements
        2. 10.2.5.2 Detailed Design Procedure
          1. 10.2.5.2.1 Basic Operation
            1. 10.2.5.2.1.1 Output Current Range and Accuracy
          2. 10.2.5.2.2 Power Consumption
      6. 10.2.6 Shunt Regulator/Reference
        1. 10.2.6.1 Design Requirements
        2. 10.2.6.2 Detailed Design Procedure
          1. 10.2.6.2.1 Programming Output/Cathode Voltage
          2. 10.2.6.2.2 Total Accuracy
          3. 10.2.6.2.3 Stability
          4. 10.2.6.2.4 Start-Up Time
        3. 10.2.6.3 Application Curves
      7. 10.2.7 Isolated Flyback with Optocoupler
        1. 10.2.7.1 Design Requirements
          1. 10.2.7.1.1 Detailed Design Procedure
            1. 10.2.7.1.1.1 ATL431LI-Q1 Biasing
            2. 10.2.7.1.1.2 Resistor Feedback Network
      8. 10.2.8 Adjustable Reference for Tracking LDO
        1. 10.2.8.1 Design Requirements
        2. 10.2.8.2 Detailed Design Procedure
          1. 10.2.8.2.1 External Capacitors
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デバイスの項目表記
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 サポート・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2.3.2 Output Voltage and Logic Input Level

For ATL431LI-Q1 to properly be used as a comparator, the logic output must be readable by the receiving logic device. This is accomplished by knowing the input high and low level threshold voltage levels, typically denoted by VIH and VIL.

As seen in Figure 24, the output low level voltage of the ATL431LI-Q1 in open-loop/comparator mode is approximately 2 V, which is typically sufficient for 5 V supplied logic. However, this does not work for 3.3 V and 1.8 V supplied logic. To accommodate this, a resistive divider can be tied to the output to attenuate the output voltage to a voltage legible to the receiving low voltage logic device.

The output high voltage of the ATL431 is equal to VSUP due to ATL431LI-Q1 being open-collector. If VSUP is much higher than the maximum input voltage tolerance of the receiving logic, the output must be attenuated to accommodate the reliability of the outgoing logic.

When using a resistive divider on the output, make sure the sum of the resistive divider (R1 and R2 in Figure 23) is much greater than RSUP to not interfere with the ability of the ATL431LI-Q1 to pull close to VSUP when turning off.