JAJSQU7A July   2023  – February 2024 AWRL1432

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 機能ブロック図
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configurations and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
      1.      11
      2.      12
      3.      13
      4.      14
      5.      15
      6.      16
      7.      17
      8.      18
      9.      19
      10.      20
      11.      21
      12.      22
      13.      23
      14.      24
      15.      25
      16.      26
      17.      27
    3.     28
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Supply Specifications
      1. 7.5.1 Power Optimized 3.3V I/O Topology
      2. 7.5.2 BOM Optimized 3.3V I/O Topology
      3. 7.5.3 Power Optimized 1.8V I/O Topology
      4. 7.5.4 BOM Optimized 1.8V I/O Topology
      5. 7.5.5 System Topologies
        1. 7.5.5.1 Power Topologies
          1. 7.5.5.1.1 BOM Optimized Mode
          2. 7.5.5.1.2 Power Optimized Mode
      6. 7.5.6 Noise and Ripple Specifications
    6. 7.6  Power Save Modes
      1. 7.6.1 Typical Power Consumption Numbers
    7. 7.7  Peak Current Requirement per Voltage Rail
    8. 7.8  RF Specification
    9. 7.9  Supported DFE Features
    10. 7.10 CPU Specifications
    11. 7.11 Thermal Resistance Characteristics
    12. 7.12 Timing and Switching Characteristics
      1. 7.12.1  Power Supply Sequencing and Reset Timing
      2. 7.12.2  Synchronized Frame Triggering
      3. 7.12.3  Input Clocks and Oscillators
        1. 7.12.3.1 Clock Specifications
      4. 7.12.4  MultiChannel buffered / Standard Serial Peripheral Interface (McSPI)
        1. 7.12.4.1 McSPI Features
        2. 7.12.4.2 SPI Timing Conditions
        3. 7.12.4.3 SPI—Controller Mode
          1. 7.12.4.3.1 Timing and Switching Requirements for SPI - Controller Mode
          2. 7.12.4.3.2 Timing and Switching Characteristics for SPI Output Timings—Controller Mode
        4. 7.12.4.4 SPI—Peripheral Mode
          1. 7.12.4.4.1 Timing and Switching Requirements for SPI - Peripheral Mode
          2. 7.12.4.4.2 Timing and Switching Characteristics for SPI Output Timings—Secondary Mode
      5. 7.12.5  RDIF Interface Configuration
        1. 7.12.5.1 RDIF Interface Timings
        2. 7.12.5.2 RDIF Data Format
      6. 7.12.6  LIN
      7. 7.12.7  General-Purpose Input/Output
        1. 7.12.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 7.12.8  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.12.8.1 Dynamic Characteristics for the CANx TX and RX Pins
      9. 7.12.9  Serial Communication Interface (SCI)
        1. 7.12.9.1 SCI Timing Requirements
      10. 7.12.10 Inter-Integrated Circuit Interface (I2C)
        1. 7.12.10.1 I2C Timing Requirements
      11. 7.12.11 Quad Serial Peripheral Interface (QSPI)
        1. 7.12.11.1 QSPI Timing Conditions
        2. 7.12.11.2 Timing Requirements for QSPI Input (Read) Timings
        3. 7.12.11.3 QSPI Switching Characteristics
      12. 7.12.12 JTAG Interface
        1. 7.12.12.1 JTAG Timing Conditions
        2. 7.12.12.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.12.12.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 機能ブロック図
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
      2. 8.3.2 Clock Subsystem
      3. 8.3.3 Transmit Subsystem
      4. 8.3.4 Receive Subsystem
      5. 8.3.5 Processor Subsystem
      6. 8.3.6 Automotive Interface
      7. 8.3.7 Host Interface
      8. 8.3.8 Main Subsystem Cortex-M4F
      9. 8.3.9 Hardware Accelerator (HWA1.2) Features
        1. 8.3.9.1 Hardware Accelerator Feature Differences Between HWA1.1 and HWA1.2
    4. 8.4 Other Subsystems
      1. 8.4.1 GPADC Channels (Service) for User Application
      2. 8.4.2 GPADC Parameters
    5. 8.5 Memory Partitioning Options
    6. 8.6 Boot Modes
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Reference Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • AMF|102
サーマルパッド・メカニカル・データ
発注情報

7.12.5.2 RDIF Data Format

GUID-9C41A4EB-5B33-4353-85C7-086CF0D2D2D0-low.jpgFigure 7-14 RDIF Data Format

  • The samples are sent one channel by one channel as shown in the diagram above. All the 12-bits of one channel are sent on 4 data lanes in 3 DDR_CLK edges, followed by next RX channel.

  • The frame clock (FRM_CLK) spans 12 DDR_CLK edges and 48 bits are sent in 1 FRM_CLK

  • The FRM_CLK can have gaps in between. This is required as the interface rate is greater than the incoming rate

  • DDR_CLK is continuous.

  • DDR_CLK is generated from 400MHz ADC CLK (one of the ADC CLKs) - selected for the DFE. It is the same 400MHz clock selected for DFE.

  • New sample always starts at the rise edge of the DDR_CLK

  • The FRM_CLK is valid for the entire data bit and is meets the Tsu/Th wrt DDR_CLK.